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* Add intrinsics, code gen, assembler and disassembler support for the SSE4a ↵Benjamin Kramer2012-05-291-0/+25
| | | | | | | | | | | extrq and insertq instructions. This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. llvm-svn: 157634
* Add retw and lretw instructions. Also, fix Intel syntax parsing for allCharles Davis2012-04-113-0/+25
| | | | | | ret instructions. llvm-svn: 154468
* Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.Craig Topper2012-04-031-0/+768
| | | | llvm-svn: 153935
* Fix generation of the address size override prefix. Add assertions forJoerg Sonnenberger2012-03-211-0/+13
| | | | | | | the invalid cases. At least 16bit operand in 64bit mode is currently not rejected in the parser. llvm-svn: 153166
* Change the X86 assembler to not require a segment register on stringKevin Enderby2012-03-131-0/+3
| | | | | | | instruction's destination operand like it does for the source operand. Also fix a typo in the comment for X86AsmParser::isSrcOp(). llvm-svn: 152654
* Added a missing error check for X86 assembly with mismatched base and indexKevin Enderby2012-03-121-0/+4
| | | | | | registers not both being 64-bit or both being 32-bit registers. llvm-svn: 152580
* Add the missing call to Error when a bad X86 scale expression is parsed.Kevin Enderby2012-03-091-0/+4
| | | | llvm-svn: 152443
* test/MC/X86/lit.local.cfg: Fix up to detect 'X86' in targets.NAKAMURA Takumi2012-03-091-0/+11
| | | | llvm-svn: 152406
* Fix the operand ordering on aliases for shld and shrd. PR12173, part 2.Eli Friedman2012-03-061-13/+21
| | | | llvm-svn: 152136
* Make aliases for shld and shrd match gas. PR12173.Eli Friedman2012-03-051-6/+11
| | | | llvm-svn: 152014
* Updated the llvm-mc disassembler C API to support for the X86 target.Kevin Enderby2012-02-231-3/+3
| | | | | | | | | | | | | | | | | | | | | rdar://10873652 As part of this I updated the llvm-mc disassembler C API to always call the SymbolLookUp call back even if there is no getOpInfo call back. If there is a getOpInfo call back that is tried first and then if that gets no information then the SymbolLookUp is called. I also made the code more robust by memset(3)'ing to zero the LLVMOpInfo1 struct before then setting SymbolicOp.Value before for the call to getOpInfo. And also don't use any values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't use any of the ReferenceType or ReferenceName values from SymbolLookUp if it returns NULL. rdar://10873563 and rdar://10873683 For the X86 target also fixed bugs so the annotations get printed. Also fixed a few places in the ARM target that was not producing symbolic operands for some instructions. rdar://10878166 llvm-svn: 151267
* Add vmfunc instruction to X86 assembler and disassembler.Craig Topper2012-02-192-0/+6
| | | | llvm-svn: 150899
* Add X86 assembler and disassembler support for AMD SVM instructions. ↵Craig Topper2012-02-182-1/+50
| | | | | | Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. llvm-svn: 150873
* Replace all instances of dg.exp file with lit.local.cfg, since all tests are ↵Eli Bendersky2012-02-162-5/+1
| | | | | | | | run with LIT now and now Dejagnu. dg.exp is no longer needed. Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches. llvm-svn: 150664
* Intel syntax. Adjust special code, used to recognize cmp<comparison ↵Devang Patel2012-01-301-0/+3
| | | | | | code>{ss,sd,ps,pd}, for intel syntax. llvm-svn: 149291
* Intel syntax. Support .intel_syntax directive.Devang Patel2012-01-301-0/+7
| | | | llvm-svn: 149270
* Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]Devang Patel2012-01-271-0/+2
| | | | llvm-svn: 149142
* Intel Syntax: Extend special hand coded logic, to recognize special ↵Devang Patel2012-01-241-0/+3
| | | | | | instructions, for intel syntax. llvm-svn: 148864
* Intel syntax: Robustify parsing of memory operand's displacement experssion.Devang Patel2012-01-231-2/+4
| | | | llvm-svn: 148737
* Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]Devang Patel2012-01-231-1/+3
| | | | llvm-svn: 148721
* Intel syntax: Parse segment registers.Devang Patel2012-01-231-0/+2
| | | | llvm-svn: 148712
* Intel syntax: Robustify register parsing.Devang Patel2012-01-201-0/+2
| | | | llvm-svn: 148591
* Intel syntax: Parse ... PTR [-8]Devang Patel2012-01-201-1/+2
| | | | llvm-svn: 148570
* Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.Devang Patel2012-01-201-1/+4
| | | | llvm-svn: 148569
* Post process 'and', 'sub' instructions and select better encoding, if available.Devang Patel2012-01-191-0/+8
| | | | llvm-svn: 148489
* Intel syntax: There is no need to create unary expr for simple negative ↵Devang Patel2012-01-191-0/+4
| | | | | | displacement. llvm-svn: 148486
* Post process 'xor', 'or' and 'cmp' instructions and select better encoding, ↵Devang Patel2012-01-191-0/+22
| | | | | | if available. llvm-svn: 148485
* Process instructions after match to select alternative encoding which may be ↵Devang Patel2012-01-181-0/+24
| | | | | | more desirable. llvm-svn: 148431
* Intel syntax: Fix parser match class to check memory operand size.Devang Patel2012-01-171-0/+2
| | | | llvm-svn: 148338
* Intel syntax: Parse "BYTE PTR [RDX + RCX]"Devang Patel2012-01-171-0/+2
| | | | llvm-svn: 148334
* Intel syntax: Do not unncessarily create plus expression for memory operand ↵Devang Patel2012-01-171-0/+2
| | | | | | displacement. llvm-svn: 148321
* Intel syntax: Ignore mnemonic aliases.Devang Patel2012-01-171-0/+8
| | | | llvm-svn: 148316
* Intel syntax: Robustify memory operand parsing.Devang Patel2012-01-171-0/+8
| | | | llvm-svn: 148312
* Add new test.Devang Patel2012-01-131-0/+10
| | | | llvm-svn: 148128
* Remove test case, as Chris suggested.Devang Patel2012-01-121-23/+0
| | | | llvm-svn: 148039
* Add test case to check intel syntax parsing.Devang Patel2012-01-121-0/+23
| | | | llvm-svn: 148034
* Make sure we correctly note the existence of an i8 immediate for vblendvps ↵Eli Friedman2011-12-151-0/+7
| | | | | | and friends, so we compute fixups correctly. PR11586. llvm-svn: 146709
* XOP instructions and encoding tests.Jan Sjödin2011-12-121-0/+584
| | | | llvm-svn: 146407
* Support for encoding all FMA4 instructions and tablegen patterns for allJan Sjödin2011-11-301-0/+378
| | | | | | remaining FMA4 instructions and intrinsics with tests. llvm-svn: 145525
* This patch contains support for encoding FMA4 instructions andBruno Cardoso Lopes2011-11-251-0/+13
| | | | | | | | | tablegen patterns for scalar FMA4 operations and intrinsic. Also add tests for vfmaddsd. Patch by Jan Sjodin llvm-svn: 145133
* X86: alias cqo to cqto.Benjamin Kramer2011-11-241-0/+1
| | | | llvm-svn: 145121
* Move test to the X86 directory, note the PR number and only run MC once.Rafael Espindola2011-10-311-0/+3
| | | | llvm-svn: 143352
* Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix andKevin Enderby2011-10-273-0/+21
| | | | | | | not depend on In32BitMode. Use the sysexitq mnemonic for the version with the REX.W prefix and only allow it only In64BitMode. rdar://9738584 llvm-svn: 143112
* Add X86 SARX, SHRX, and SHLX instructions.Craig Topper2011-10-231-0/+49
| | | | llvm-svn: 142779
* Add X86 RORX instructionCraig Topper2011-10-231-0/+32
| | | | llvm-svn: 142741
* Rename PEXTR to PEXT. Add intrinsics for BMI instructions.Craig Topper2011-10-191-8/+8
| | | | llvm-svn: 142480
* Add X86 PEXTR and PDEP instructions.Craig Topper2011-10-161-0/+32
| | | | llvm-svn: 142141
* Add X86 BZHI instruction as well as BMI2 feature detection.Craig Topper2011-10-161-0/+16
| | | | llvm-svn: 142122
* Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang ↵Chris Lattner2011-10-161-0/+3
| | | | | | | | | | | | | | | does. Enhance the X86 asmparser to produce ranges in the one case that was annoying me, for example: test.s:10:15: error: invalid operand for instruction movl 0(%rax), 0(%edx) ^~~~~~~ It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use ranges where appropriate if someone is interested. llvm-svn: 142106
* Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand ↵Craig Topper2011-10-161-0/+16
| | | | | | 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen llvm-svn: 142105
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