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* [x86] Fix JCXZ,JECXZ_32 for 16-bit modeDavid Woodhouse2014-01-081-0/+8
| | | | | | | JCXZ should have the 0x67 prefix only if we're in 32-bit mode, so make that appropriately conditional. And JECXZ needs the prefix instead. llvm-svn: 198757
* [x86] Disambiguate RET[QL] and fix aliases for 16-bit modeDavid Woodhouse2014-01-081-0/+54
| | | | | | | | | | I couldn't see how to do this sanely without splitting RETQ from RETL. Eric says: "sad about the inability to roundtrip them now, but...". I have no idea what that means, but perhaps it wants preserving in the commit comment. llvm-svn: 198756
* [x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliasesDavid Woodhouse2014-01-083-16/+64
| | | | llvm-svn: 198755
* [x86] Add JMP16[rm],CALL16[rm] instructions, and fix up aliasesDavid Woodhouse2014-01-082-0/+34
| | | | llvm-svn: 198754
* [x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit modeDavid Woodhouse2014-01-082-2/+59
| | | | llvm-svn: 198753
* [x86] Add OpSize16 to instructions that need itDavid Woodhouse2014-01-081-0/+277
| | | | | | | | | This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
* Add OpSize16 bit, for instructions which need 0x66 prefix in 16-bit modeCraig Topper2014-01-061-0/+170
| | | | | | | | | | | | | | | | | The 0x66 prefix toggles between 16-bit and 32-bit addressing mode. So in 32-bit mode it is used to switch to 16-bit addressing mode for the following instruction, while in 16-bit mode it's the other way round — it's used to switch to 32-bit mode instead. Thus, emit the 0x66 prefix byte for OpSize only in 32-bit (and 64-bit) mode, and introduce a new OpSize16 bit which is used in 16-bit mode instead. This is just the basic infrastructure for that change; a subsequent patch will add the new OpSize16 bit to the 32-bit instructions that need it. Patch from David Woodhouse. llvm-svn: 198586
* [x86] Add basic support for .code16Craig Topper2014-01-062-0/+267
| | | | | | | | | | | This is not really expected to work right yet. Mostly because we will still emit the OpSize (0x66) prefix in all the wrong places, along with a number of other corner cases. Those will all be fixed in the subsequent commits. Patch from David Woodhouse. llvm-svn: 198584
* Fix ModR/M byte output for 16-bit addressing modes (PR18220)Craig Topper2014-01-051-1/+7
| | | | | | | | | Add some tests to validate correct register selection, including a fix to an existing test which was requiring the *wrong* output. Patch from David Woodhouse. llvm-svn: 198566
* Un-revert: the buildbot failure in LLVM on lld-x86_64-win7 had me withKevin Enderby2013-12-191-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this commit as the only one on the Blamelist so I quickly reverted this. However it was actually Nick's change who has since fixed that issue. Original commit message: Changed the X86 assembler for intel syntax to work with directional labels. The X86 assembler as a separate code to parser the intel assembly syntax in X86AsmParser::ParseIntelOperand(). This did not parse directional labels. And if something like 1f was used as a branch target it would get an "Unexpected token" error. The fix starts in X86AsmParser::ParseIntelExpression() in the case for AsmToken::Integer, it needs to grab the IntVal from the current token then look for a 'b' or 'f' following an Integer. Then it basically needs to do what is done in AsmParser::parsePrimaryExpr() for directional labels. It saves the MCExpr it creates in the IntelExprStateMachine in the Sym field. When it returns to X86AsmParser::ParseIntelOperand() it looks for a non-zero Sym field in the IntelExprStateMachine and if set it creates a memory operand not an immediate operand it would normally do for the Integer. rdar://14961158 llvm-svn: 197744
* Revert my change to the X86 assembler for intel syntax to work withKevin Enderby2013-12-191-16/+0
| | | | | | directional labels. Because it doesn't work for windows :) llvm-svn: 197731
* Changed the X86 assembler for intel syntax to work with directional labels.Kevin Enderby2013-12-191-0/+16
| | | | | | | | | | | | | | | | | | | | | | | The X86 assembler has a separate code to parser the intel assembly syntax in X86AsmParser::ParseIntelOperand(). This did not parse directional labels. And if something like 1f was used as a branch target it would get an "Unexpected token" error. The fix starts in X86AsmParser::ParseIntelExpression() in the case for AsmToken::Integer, it needs to grab the IntVal from the current token then look for a 'b' or 'f' following the Integer. Then it basically needs to do what is done in AsmParser::parsePrimaryExpr() for directional labels. It saves the MCExpr it creates in the IntelExprStateMachine in the Sym field. When it returns to X86AsmParser::ParseIntelOperand() it looks for a non-zero Sym field in the IntelExprStateMachine and if set it creates a memory operand not an immediate operand it would normally do for the Integer. rdar://14961158 llvm-svn: 197728
* Grow the stackmap/patchpoint format to hold 64-bit IDs.Andrew Trick2013-12-131-17/+17
| | | | llvm-svn: 197255
* [Stackmap] Specify the triple and cpu to fix the unit test.Juergen Ributzka2013-12-041-1/+1
| | | | llvm-svn: 196339
* [Stackmap] Emit multi-byte nops for X86.Juergen Ributzka2013-12-041-0/+47
| | | | llvm-svn: 196334
* Use -triple to fix the test on non-ELF hosts.Rafael Espindola2013-11-251-16/+16
| | | | llvm-svn: 195682
* Don't use nopl in cpus that don't support it.Rafael Espindola2013-11-251-2/+25
| | | | | | | | | | | | | | | Patch by Mikulas Patocka. I added the test. I checked that for cpu names that gas knows about, it also doesn't generate nopl. The modified cpus: i686 - there are i686-class CPUs that don't have nopl: Via c3, Transmeta Crusoe, Microsoft VirtualBox - see https://bbs.archlinux.org/viewtopic.php?pid=775414 k6, k6-2, k6-3, winchip-c6, winchip2 - these are 586-class CPUs via c3 c3-2 - see https://bugs.archlinux.org/task/19733 as a proof that Via c3 and c3-Nehemiah don't have nopl llvm-svn: 195679
* X86: Assembly files with .cfi_cfa_def shouldn't hit llvm_unreachable()Jim Grosbach2013-11-081-0/+73
| | | | | | | | | | On darwin, when trying to create compact unwind info, a .cfi_cfa_def directive would case an llvm_unreachable() to be hit. Back off when we see this directive and generate the regular DWARF style eh_frame. rdar://15406518 llvm-svn: 194285
* Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps ↵Craig Topper2013-10-143-13/+13
| | | | | | instructions to parse either GR32 or GR64 without resorting to duplicating instructions. llvm-svn: 192567
* Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the ↵Craig Topper2013-10-141-0/+8
| | | | | | disassembler tables. Add PINSRWrr64i to complement the AVX version. llvm-svn: 192565
* Allow non-AVX form of pmovmskb to take a GR64 operand.Craig Topper2013-10-101-0/+4
| | | | llvm-svn: 192341
* Remove some instructions that existed to provide aliases to the assembler. ↵Craig Topper2013-10-082-3/+16
| | | | | | Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. llvm-svn: 192171
* Teach X86 asm parser that VMOVAPSrr and other VEX-encoded register to ↵Craig Topper2013-10-071-0/+56
| | | | | | | | register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not. This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior and instruction selection already does this. llvm-svn: 192088
* Add XOP disassembler support. Fixes PR13933.Craig Topper2013-10-031-1/+1
| | | | llvm-svn: 191874
* Revert accidental commit.Craig Topper2013-09-291-1/+41
| | | | llvm-svn: 191633
* Change type of XOP flag in code emitters to a bool. Remove a some unneeded ↵Craig Topper2013-09-291-41/+1
| | | | | | cases from switch. llvm-svn: 191632
* Adding intrinsics to the llvm backend for TBM instruction set.Yunzhong Gao2013-09-271-0/+196
| | | | | | Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 llvm-svn: 191539
* Fixing Intel format of the vshufpd instruction.Yunzhong Gao2013-09-271-0/+2
| | | | | | Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759 llvm-svn: 191481
* Add the remaining Intel SHA instructionsBen Langmuir2013-09-141-0/+52
| | | | | | | Also assembly/disassembly tests, and for sha256rnds2, aliases with an explicit xmm0 dependency. llvm-svn: 190754
* Partial support for Intel SHA Extensions (sha1rnds4)Ben Langmuir2013-09-121-0/+8
| | | | | | | | | Add basic assembly/disassembly support for the first Intel SHA instruction 'sha1rnds4'. Also includes feature flag, and test cases. Support for the remaining instructions will follow in a separate patch. llvm-svn: 190611
* AVX-512: implemented extractelement with variable index.Elena Demikhovsky2013-09-121-1/+9
| | | | | | Added parsing of mask register and "zeroing" semantic, like {%k1} {z}. llvm-svn: 190595
* [ms-inline asm] Support offsets after segment registersDavid Majnemer2013-08-271-0/+6
| | | | | | | | | | | | | | Summary: MASM let's you do stuff like 'MOV FS:20, EAX' and 'MOV EAX, FS:20' Reviewers: craig.topper, rnk Reviewed By: rnk CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1470 llvm-svn: 189407
* AVX-512: Added SHIFT instructions.Elena Demikhovsky2013-08-211-0/+16
| | | | llvm-svn: 188899
* [tests] Cleanup initialization of test suffixes.Daniel Dunbar2013-08-162-4/+0
| | | | | | | | | | | | | | | | | - Instead of setting the suffixes in a bunch of places, just set one master list in the top-level config. We now only modify the suffix list in a few suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py). - Aside from removing the need for a bunch of lit.local.cfg files, this enables 4 tests that were inadvertently being skipped (one in Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been XFAILED). - This commit also fixes a bunch of config files to use config.root instead of older copy-pasted code. llvm-svn: 188513
* EVEX and compressed displacement encoding for AVX512Elena Demikhovsky2013-08-011-0/+21
| | | | llvm-svn: 187576
* Add test cases for the various instruction alias and Intel syntax fixes that ↵Craig Topper2013-07-263-17/+380
| | | | | | have gone in lately. llvm-svn: 187188
* Don't let x86 asm printer use the no operand movsd alias. It should use the ↵Craig Topper2013-07-232-11/+11
| | | | | | normal movsl instead. llvm-svn: 186924
* Fix the move to/from accumulator register instructions that use a full 64-bitKevin Enderby2013-07-221-0/+32
| | | | | | | | absolute address encoded in the instruction. rdar://8612627 and rdar://14299221 llvm-svn: 186878
* Recommit r186813: More Intel syntax alias fixes. With the addition of ↵Craig Topper2013-07-221-15/+15
| | | | | | suppressing some of the aliases from being emitted by the asm printer. llvm-svn: 186869
* Prefix failing commands with not to make clear they are expected to fail.Rafael Espindola2013-07-036-6/+6
| | | | llvm-svn: 185554
* Add support for encoding the HLE XACQUIRE and XRELEASE prefixes.Stefanus Du Toit2013-06-181-0/+9
| | | | | | | | For decoding, keep the current behavior of always decoding these as their REP versions. In the future, this could be improved to recognize the cases where these behave as XACQUIRE and XRELEASE and decode them as such. llvm-svn: 184207
* X86: Make the cmov aliases work with intel syntax too.Benjamin Kramer2013-06-131-0/+29
| | | | llvm-svn: 183907
* [ms-inline asm] Fix a crasher when we fail on a direct match.Chad Rosier2013-05-101-0/+3
| | | | | | | | | | | | | | | | | | The issue was that the MatchingInlineAsm and VariantID args to the MatchInstructionImpl function weren't being set properly. Specifically, when parsing intel syntax, the parser thought it was parsing inline assembly in the at&t dialect; that will never be the case. The crash was caused when the emitter tried to emit the instruction, but the operands weren't set. When parsing inline assembly we only set the opcode, not the operands, which is used to lookup the instruction descriptor. rdar://13854391 and PR15945 Also, this commit reverts r176036. Now that we're correctly parsing the intel syntax the pushad/popad don't match properly. I've reimplemented that fix using a MnemonicAlias. llvm-svn: 181620
* [x86AsmParser] It's valid to stop parsing an operand at an immediate.Chad Rosier2013-05-091-0/+2
| | | | | | rdar://13854369 and PR15944 llvm-svn: 181564
* Add test case for PR15779, which has previously been fixed.Chad Rosier2013-04-221-1/+2
| | | | llvm-svn: 180058
* [ms-inline asm] Apply the condition code mnemonic aliases to both the Intel andChad Rosier2013-04-181-0/+30
| | | | | | | AT&T dialect. Test case for r179804 as well. rdar://13674398 and PR13340. llvm-svn: 179813
* [ms-inline asm] Add support for the minus unary operator. Previously, we wereChad Rosier2013-04-171-1/+8
| | | | | | | | | | | unable to handle cases such as __asm mov eax, 8*-8. This patch also attempts to simplify the state machine. Further, the error reporting has been improved. Test cases included, but more will be added to the clang side shortly. rdar://13668445 llvm-svn: 179719
* Add CLAC/STAC instruction encoding/decoding supportMichael Liao2013-04-111-0/+8
| | | | | | | As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. llvm-svn: 179266
* [ms-inline asm] Add support for numeric displacement expressions in bracketedChad Rosier2013-04-051-1/+38
| | | | | | | | | | | | | | | | | | | | | | memory operands. Essentially, this layers an infix calculator on top of the parsing state machine. The scale on the index register is still expected to be an immediate __asm mov eax, [eax + ebx*4] and will not work with more complex expressions. For example, __asm mov eax, [eax + ebx*(2*2)] The plus and minus binary operators assume the numeric value of a register is zero so as to not change the displacement. Register operands should never be an operand for a multiply or divide operation; the scale*indexreg expression is always replaced with a zero on the operand stack to prevent such a case. rdar://13521380 llvm-svn: 178881
* Add support of RDSEED defined in AVX2 extensionMichael Liao2013-03-281-0/+49
| | | | llvm-svn: 178314
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