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* [MC] Teach ELFObjectWriter that parse-time variables do not appear inNirav Dave2019-03-041-0/+3
| | | | | | symbol table. llvm-svn: 355325
* X86AsmParser AVX-512: Return error instead of hitting assertCraig Topper2019-02-191-0/+3
| | | | | | | | | | When parsing a sequence of tokens beginning with {, it will hit an assert and crash if the token afterwards is not an identifier. Instead of this, return a more verbose error as seen elsewhere in the function. Patch by Brandon Jones (BrandonTJones) Differential Revision: https://reviews.llvm.org/D57375 llvm-svn: 354356
* Move some llvm-mc tests where they belongMatt Arsenault2019-02-051-0/+43
| | | | llvm-svn: 353211
* [X86] Print all register forms of x87 fadd/fsub/fdiv/fmul as having two ↵Craig Topper2019-02-048-118/+118
| | | | | | | | | | arguments where on is %st. All of these instructions consume one encoded register and the other register is %st. They either write the result to %st or the encoded register. Previously we printed both arguments when the encoded register was written. And we printed one argument when the result was written to %st. For the stack popping forms the encoded register is always the destination and we didn't print both operands. This was inconsistent with gcc and objdump and just makes the output assembly code harder to read. This patch changes things to always print both operands making us consistent with gcc and objdump. The parser should still be able to handle the single register forms just as it did before. This also matches the GNU assembler behavior. llvm-svn: 353061
* [X86] Print %st(0) as %st when its implicit to the instruction. Continue ↵Craig Topper2019-02-047-121/+121
| | | | | | | | printing it as %st(0) when its encoded in the instruction. This is a step back from the change I made in r352985. This appears to be more consistent with gcc and objdump behavior. llvm-svn: 353015
* Revert r352985 "[X86] Print %st(0) as %st to match what gcc inline asm uses ↵Craig Topper2019-02-049-175/+175
| | | | | | | | | | as the clobber name to make MS inline asm work correctly" Looking into gcc and objdump behavior more this was overly aggressive. If the register is encoded in the instruction we should print %st(0), if its implicit we should print %st. I'll be making a more directed change in a future patch. llvm-svn: 353013
* [X86] Print %st(0) as %st to match what gcc inline asm uses as the clobber ↵Craig Topper2019-02-039-175/+175
| | | | | | | | | | | | | | | | | | | name to make MS inline asm work correctly Summary: When calculating clobbers for MS style inline assembly we fail if the asm clobbers stack top because we print st(0) and try to pass it through the gcc register name check. This was found with when I attempted to make a emms/femms clobber all ST registers. If you use emms/femms in MS inline asm we would try to use st(0) as the clobber name but clang would think that wasn't a valid clobber name. This also matches what objdump disassembly prints. It's also what is printed by gcc -S. Reviewers: RKSimon, rnk, efriedma, spatel, andreadb, lebedev.ri Reviewed By: rnk Subscribers: eraman, gbedwell, lebedev.ri, llvm-commits Differential Revision: https://reviews.llvm.org/D57621 llvm-svn: 352985
* [X86][SSE]: Adding full coverage of MC encoding tests for the SSE isa sets.<NFC>Craig Topper2019-02-0220-170/+15824
| | | | | | | | | | | | | | | | | | | | | | Summary: NFC. Adding MC regressions tests to cover all the SSE ISA sets as follows: SSE, SSE2, SSE3, SSE4, SSE42, SSEMXCSR, SSE_PREFETCH, SSSE3 This patch is part of a larger task to cover MC encoding of all X86 ISA Sets. See revision: https://reviews.llvm.org/D39952 Patch by Gadi Haber and Wang Tianqing Reviewers: RKSimon, zvi, craig.topper, AndreiGrischenko, gadi.haber, LuoYuanke Reviewed By: craig.topper Subscribers: jfb, llvm-commits Differential Revision: https://reviews.llvm.org/D40387 llvm-svn: 352955
* [X86][AVX512F_SCALAR]: Adding full coverage of MC encoding for the ↵Craig Topper2019-01-222-0/+22392
| | | | | | | | | | | AVX512F_SCALAR isa sets. NFC Adding MC regressions tests to cover the AVX512F_SCALAR isa sets. This patch is part of a larger task to cover MC encoding of all X86 isa sets started in revision: https://reviews.llvm.org/D39952 Differential Revision: https://reviews.llvm.org/D41174 llvm-svn: 351874
* [MC][X86] Add test case for invalid use of "(%dx)" operand.Nirav Dave2019-01-141-0/+4
| | | | llvm-svn: 351094
* Replace "no-frame-pointer-*" function attributes with "frame-pointer"Francis Visoiu Mistrih2019-01-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Part of the effort to refactoring frame pointer code generation. We used to use two function attributes "no-frame-pointer-elim" and "no-frame-pointer-elim-non-leaf" to represent three kinds of frame pointer usage: (all) frames use frame pointer, (non-leaf) frames use frame pointer, (none) frame use frame pointer. This CL makes the idea explicit by using only one enum function attribute "frame-pointer" Option "-frame-pointer=" replaces "-disable-fp-elim" for tools such as llc. "no-frame-pointer-elim" and "no-frame-pointer-elim-non-leaf" are still supported for easy migration to "frame-pointer". tests are mostly updated with // replace command line args ‘-disable-fp-elim=false’ with ‘-frame-pointer=none’ grep -iIrnl '\-disable-fp-elim=false' * | xargs sed -i '' -e "s/-disable-fp-elim=false/-frame-pointer=none/g" // replace command line args ‘-disable-fp-elim’ with ‘-frame-pointer=all’ grep -iIrnl '\-disable-fp-elim' * | xargs sed -i '' -e "s/-disable-fp-elim/-frame-pointer=all/g" Patch by Yuanfang Chen (tabloid.adroit)! Differential Revision: https://reviews.llvm.org/D56351 llvm-svn: 351049
* [X86] Fix incomplete handling of register-assigned variables in parsing.Nirav Dave2019-01-112-0/+439
| | | | | | | | | | | | | | Teach x86 assembly operand parsing to distinguish between assembler variable assigned to named registers and those assigned to immediate values. Reviewers: rnk, nickdesaulniers, void Subscribers: hiraditya, jyknight, llvm-commits Differential Revision: https://reviews.llvm.org/D56287 llvm-svn: 350966
* [llvm-objdump] - Implement -z/--disassemble-zeroes.George Rimar2019-01-101-0/+81
| | | | | | | | | | | | | | This is https://bugs.llvm.org/show_bug.cgi?id=37151, GNU objdump spec says that "Normally the disassembly output will skip blocks of zeroes.", but currently, llvm-objdump prints them. The patch implements the -z/--disassemble-zeroes option and switches the default to always skip blocks of zeroes. Differential revision: https://reviews.llvm.org/D56083 llvm-svn: 350823
* [X86][Darwin] Emit compact-unwind for register-sized stack adjustmentsFrancis Visoiu Mistrih2019-01-081-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For stack frames on the size of a register in x86, a code size optimization emits "push rax/eax" instead of "sub" for stack allocation. For example: foo: .cfi_startproc BB#0: pushq %rax Ltmp0: .cfi_def_cfa_offset 16 ... .cfi_endproc However, we are falling back to DWARF in this case because we cannot encode %rax as a saved register. This requirement is wrong, since we don't care about the contents of %rax, it is the equivalent of a sub. In order to specify that we care about the contents of %rax, we would need a .cfi_offset %rax, <offset>. It's also overzealous in the case where there are pushes for callee saved registers followed by a "push rax/eax" instead of "sub", in which case we should also be able to encode the callee saved regs and everything else using compact unwind. Patch authored by Bruno Cardoso Lopes. Differential Revision: https://reviews.llvm.org/D13793 llvm-svn: 350623
* [X86] Adding full coverage of MC encoding for the XOP and LWP ISAs.Craig Topper2019-01-024-0/+6946
| | | | | | | | | Adding MC regressions tests to cover the XOP isa set. This patch is part of a larger task to cover MC encoding of all X86 isa sets started in revision: https://reviews.llvm.org/D39952 Differential Revision: https://reviews.llvm.org/D41392 llvm-svn: 350237
* [MC] Separate masm integer literal lexer support from inline asmReid Kleckner2018-10-242-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This renames the IsParsingMSInlineAsm member variable of AsmLexer to LexMasmIntegers and moves it up to MCAsmLexer. This is the only behavior controlled by that variable. I added a public setter, so that it can be set from outside or from the llvm-mc command line. We may need to arrange things so that users can get this behavior from clang, but that's future work. I also put additional hex literal lexing functionality under this flag to fix PR32973. It appears that this hex literal parsing wasn't intended to be enabled in non-masm-style blocks. Now, masm integers (0b1101 and 0ABCh) work in __asm blocks from clang, but 0b label references work when using .intel_syntax in standalone .s files. However, 0b label references will *not* work from __asm blocks in clang. They will work from GCC inline asm blocks, which it sounds like is important for Crypto++ as mentioned in PR36144. Essentially, we only lex masm literals for inline asm blobs that use intel syntax. If the .intel_syntax directive is used inside a gnu-style inline asm statement, masm literals will not be lexed, which is compatible with gas and llvm-mc standalone .s assembly. This fixes PR36144 and PR32973. Reviewers: Gerolf, avt77 Subscribers: eraman, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D53535 llvm-svn: 345189
* X86: add alias for pushfw/popfw in Intel modeTim Northover2018-10-221-0/+5
| | | | | | | | | A while ago we changed pushf and popf in Intel mode to generate pushfq and popfq. Unfortunately that left us with no way to get the 16-bit encoding in Intel mode so this patch adds pushfw and popfw as aliases there. llvm-svn: 344949
* [MC][DWARF][AsmParser] Ensure nested CFI frames are diagnosed.Kristina Brooks2018-10-192-4/+29
| | | | | | | | | | | | | | | | | | This avoids a crash (with asserts) or bad codegen (without asserts) in Dwarf streamer later on. This patch fixes this condition in MCStreamer and propogates SMLoc down when it's available with an added bonus of source locations for those specific types of errors. Further patches could use similar improvements as currently most non-Windows CFI directives lack an SMLoc parameter. Modified an existing test to verify source location propogation and added an object-file version of it to verify that it does not crash in addition to a standalone test to only ensure it does not crash. Differential Revision: https://reviews.llvm.org/D51695 llvm-svn: 344781
* [X86][Assembler] Allow %eip as a register in 32-bit mode for .cfi directives.Craig Topper2018-09-062-2/+26
| | | | | | | | | | This basically reverts a change made in r336217, but improves the text of the error message for not allowing IP-relative addressing in 32-bit mode. Fixes PR38826. Patch by Iain Sandoe. llvm-svn: 341512
* [MC][X86] Enhance X86 Register expression handling to more closely match GCC.Nirav Dave2018-08-161-7/+11
| | | | | | | | | | | | | | | | Allow the comparison of x86 registers in the evaluation of assembler directives. This generalizes and simplifies the extension from r334022 to catch another case found in the Linux kernel. Reviewers: rnk, void Reviewed By: rnk Subscribers: hiraditya, nickdesaulniers, llvm-commits Differential Revision: https://reviews.llvm.org/D50795 llvm-svn: 339895
* [X86][AsmParser] Don't consider %eip as a valid register outside of 32-bit mode.Craig Topper2018-07-031-2/+2
| | | | | | | | This might make the error message added in r335668 unneeded, but I'm not sure yet. The check for RIP is technically unnecessary since RIP is in GR64, but that fact is kind of surprising so be explicit. llvm-svn: 336217
* Move `REQUIRES:` line to the topFangrui Song2018-06-261-1/+1
| | | | llvm-svn: 335635
* [X86] Allow base and index for gather instructions to appear in other order ↵Craig Topper2018-06-251-0/+5
| | | | | | for Intel syntax. llvm-svn: 335500
* [X86] Make %eiz usage in 64-bit mode, force a 0x67 address size prefix. Fix ↵Craig Topper2018-06-231-6/+10
| | | | | | some test CHECK lines. llvm-svn: 335414
* [X86][AsmParser] Improve base/index register checks.Craig Topper2018-06-231-0/+16
| | | | | | | | | -Ensure EIP isn't used with an index reigster. -Ensure EIP isn't used as index register. -Ensure base register isn't a vector register. -Ensure eiz/riz usage matches the size of their base register. llvm-svn: 335412
* [X86][AsmParser] Keep track of whether an explicit scale was specified while ↵Craig Topper2018-06-221-0/+6
| | | | | | | | | | parsing an address in Intel syntax. Use it for improved error checking. This allows us to check these: -16-bit addressing doesn't support scale so we should error if we find one there. -Multiplying ESP/RSP by a scale even if the scale is 1 should be an error because ESP/RSP can't be an index. llvm-svn: 335398
* [X86][AsmParser] In Intel syntax make sure we support ESP/RSP being the ↵Craig Topper2018-06-221-0/+8
| | | | | | | | | | second register in memory expressions like [EAX+ESP]. By default, the second register gets assigned to the index register slot. But ESP can't be an index register so we need to swap it with the other register. There's still a slight bug that we allow [EAX+ESP*1]. The existence of the multiply even though its with 1 should force ESP to the index register and trigger an error, but it doesn't currently. llvm-svn: 335394
* [X86] Don't accept (%si,%bp) 16-bit address expressions.Craig Topper2018-06-224-2/+20
| | | | | | | | | | The second register is the index register and should only be %si or %di if used with a base register. And in that case the base register should be %bp or %bx. This makes us compatible with gas. We do still need to support both orders with Intel syntax which uses [bp+si] and [si+bp] llvm-svn: 335384
* [X86][AsmParser] Allow (%bp,%si) and (%bp,%di) to be encoded without using a ↵Craig Topper2018-06-221-0/+4
| | | | | | | | zero displacement. (%bp) can't be encoded without a displacement. The encoding is instead used for displacement alone. So a 1 byte displacement of 0 must be used. But if there is an index register we can encode without a displacement. llvm-svn: 335379
* [X86][AsmParser] Check for invalid 16-bit base register in Intel syntax.Craig Topper2018-06-221-0/+2
| | | | llvm-svn: 335373
* [X86] Don't allow ESP/RSP to be used as an index register in assembly.Craig Topper2018-06-221-0/+8
| | | | | | Fixes PR37892 llvm-svn: 335370
* [X86] Add '.s' aliases to the assembler for the various redundant move ↵Craig Topper2018-06-182-48/+120
| | | | | | | | | | encodings to match gas and our EVEX instructions. We already have these aliases for EVEX enocded instructions, but not for the GPR, MMX, SSE, and VEX versions. Also remove the vpextrw.s EVEX alias. That's not something gas implements. llvm-svn: 334922
* [X86] Move the 'vmovq.s' and similar assembly strings for EVEX vector moves ↵Craig Topper2018-06-186-442/+442
| | | | | | | | | | with reversed operands to InstAliases. The .s assembly strings allow the reversed forms to be targeted from assembly which matches gas behavior. But when printing the instructions we should print them without the .s to match other tooling like objdump. By using InstAliases we can use the normal string in the instruction and just hide it from the assembly parser. Ideally we'd add the .s versions to the legacy SSE and VEX versions as well for full compatibility with gas. Not sure how we got to state where only EVEX was supported. llvm-svn: 334920
* [TableGen] Prevent double flattening of InstAlias asm strings in the asm ↵Craig Topper2018-06-181-0/+8
| | | | | | | | | | | | matcher emitter. Unlike CodeGenInstruction, CodeGenInstAlias was flatting asm strings in its constructor. For instructions it was the users responsibility to flatten the string. AsmMatcherEmitter didn't know this and treated them the same. This caused double flattening of InstAliases. This is mostly harmless unless the desired assembly string contains curly braces. The second flattening wouldn't know to ignore these and would remove the curly braces. And for variant 1 it would remove the contents of them as well. To mitigate this, this patch makes removes the flattening from the CodeGenIntAlias constructor and modifies AsmWriterEmitter to account for the flattening not having been done. llvm-svn: 334919
* [X86] Add encoding tests for avx5124fmaps and avx5124vnni instructions.Craig Topper2018-06-112-0/+91
| | | | | | I forgot to git add these in r333812 llvm-svn: 334387
* [MC] Pass MCSubtargetInfo to fixupNeedsRelaxation and applyFixupPeter Smith2018-06-061-0/+16
| | | | | | | | | | | | | | | | | | On targets like Arm some relaxations may only be performed when certain architectural features are available. As functions can be compiled with differing levels of architectural support we must make a judgement on whether we can relax based on the MCSubtargetInfo for the function. This change passes through the MCSubtargetInfo for the function to fixupNeedsRelaxation so that the decision on whether to relax can be made per function. In this patch, only the ARM backend makes use of this information. We must also pass the MCSubtargetInfo to applyFixup because some fixups skip error checking on the assumption that relaxation has occurred, to prevent code-generation errors applyFixup must see the same MCSubtargetInfo as fixupNeedsRelaxation. Differential Revision: https://reviews.llvm.org/D44928 llvm-svn: 334078
* [MC][X86] Allow assembler variable assignment to register name.Nirav Dave2018-06-051-0/+16
| | | | | | | | | | | | | | | | | | | Summary: Allow extended parsing of variable assembler assignment syntax and modify X86 to permit VAR = register assignment. As we emit these as .set directives when possible, we inline such expressions in output assembly. Fixes PR37425. Reviewers: rnk, void, echristo Reviewed By: rnk Subscribers: nickdesaulniers, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D47545 llvm-svn: 334022
* Implemented sane default for llvm-objdump's relocation Value formatDaniel Cederman2018-06-011-1/+1
| | | | | | | | | | | | | | | | | | | | | Summary: "Unknown" for platforms that were not manually added into the switch did not make sense at all. Now it prints Target + addend for all elf-machines that were not explicitly mentioned. Addresses PR21059 and PR25124. Original author: fedor.sergeev Reviewers: jyknight, espindola, fedor.sergeev Reviewed By: jyknight Subscribers: eraman, dcederman, jfb, dschuff, aheejin, llvm-commits Differential Revision: https://reviews.llvm.org/D36464 llvm-svn: 333726
* [x86] Introduce the enclv instructionGabor Buella2018-05-085-29/+24
| | | | | | | | | | | | | | Summary: and use the -msgx flag as a requirement for the SGX instructions. Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D46436 llvm-svn: 331742
* [x86] Introduce the pconfig instructionGabor Buella2018-05-082-0/+8
| | | | | | | | | | Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D46430 llvm-svn: 331739
* [X86] movdiri and movdir64b instructionsGabor Buella2018-05-013-0/+56
| | | | | | | | | | Reviewers: spatel, craig.topper, RKSimon Reviewed By: craig.topper, RKSimon Differential Revision: https://reviews.llvm.org/D45983 llvm-svn: 331248
* [X86] Remove 'opaque ptr' from the intel syntax parser and printer.Craig Topper2018-05-011-2/+2
| | | | | | | | Previously for instructions like fxsave we would print "opaque ptr" as part of the memory operand. Now we print nothing. We also no longer accept "opaque ptr" in the parser. We still accept any size to be specified for these instructions, but we may want to consider only parsing when no explicit size is specified. This what gas does. llvm-svn: 331243
* [X86] Add a Requires<[In64BitMode]> to FARJMP64Craig Topper2018-04-302-1/+4
| | | | | | Otherwise we can try to assemble it in 32-bit mode and throw an assert in the encoder. llvm-svn: 331161
* [X86] Remove support for accepting 'fnstsw %eax' and 'fnstsw %al'.Craig Topper2018-04-302-8/+0
| | | | | | I assume this was done because gas accepted it at one point, but current versions of gas don't. llvm-svn: 331154
* [X86] Make 64-bit sysret/sysexit not ambiguous in Intel assembly syntax.Craig Topper2018-04-291-0/+9
| | | | | | This also makes it default to the 32-bit non REX.W version in 64-bit mode. This seems to be more consistent with gas. llvm-svn: 331149
* [X86] Add suffixes to the LGDT/LIDT/SGDT/SIDT mnemonics in Intel syntax. Add ↵Craig Topper2018-04-291-0/+18
| | | | | | | | | | aliases based on 16/32-bit mode to choose the default. This allows the instruction selection to follow mode in Intel syntax. And allows a suffix to be used to change size. This matches gas behavior from what I could tell. llvm-svn: 331138
* [X86] Remove SLDT64m instruction.Craig Topper2018-04-292-23/+11
| | | | | | | | It doesn't really exist. The instruction always writes 16-bits of memory. Putting a REX.w on it won't change anything. While I was touching the encoding tests to remove it, I added some other missing register form test cases. llvm-svn: 331135
* [X86] Remove REX.W from 64-bit mode BND instructions.Craig Topper2018-04-281-6/+6
| | | | | | As far as I can tell from the docs, the instructions are automatically 64-bit in 64-bit mode. We don't need REX.W. llvm-svn: 331102
* [X86] Rename BNDMOV instructions and hide redundant instruction encoding ↵Craig Topper2018-04-281-1/+1
| | | | | | | | | | | | from the assembler. Favor the 0x1a encoding for register/register move to match gas. The instructions used RM and MR in their name along with rr/rm/mr at the end. To make more consistent with other instructions remove the RM/MR and use rr/rm/mr/rr_REV. Hide the _REV encoding from the assembler but leave it for the disassembler. llvm-svn: 331101
* [X86] Revert r330638 - accidental commitGabor Buella2018-04-233-56/+0
| | | | llvm-svn: 330640
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