summaryrefslogtreecommitdiffstats
path: root/llvm/test/MC/X86
Commit message (Collapse)AuthorAgeFilesLines
...
* [X86] Add SAL mnemonics for Intel syntaxMarina Yatsina2015-08-111-0/+3
| | | | | | | | SAL and SHL instructions perform the same operation Differential Revision: http://reviews.llvm.org/D11882 llvm-svn: 244588
* [X86] Fix REPE, REPZ, REPNZ for intel syntaxMarina Yatsina2015-08-111-0/+13
| | | | | | | | | REPE, REPZ, REPNZ, REPNE should have mnemonics for Intel syntax as well. Currently using these instructions causes compilation errors for Intel syntax. Differential Revision: http://reviews.llvm.org/D11794 llvm-svn: 244584
* [X86] Fix imul alias for intel syntaxMarina Yatsina2015-08-111-0/+7
| | | | | | | | | The "imul reg, imm" alias is not defined for intel syntax. In intel syntax there is no w/l/q suffix for the imul instruction. Differential Revision: http://reviews.llvm.org/D11887 llvm-svn: 244582
* DI: Disallow uniquable DICompileUnitsDuncan P. N. Exon Smith2015-08-031-1/+1
| | | | | | | | | | | | | | | | | | Since r241097, `DIBuilder` has only created distinct `DICompileUnit`s. The backend is liable to start relying on that (if it hasn't already), so make uniquable `DICompileUnit`s illegal and automatically upgrade old bitcode. This is a nice cleanup, since we can remove an unnecessary `DenseSet` (and the associated uniquing info) from `LLVMContextImpl`. Almost all the testcases were updated with this script: git grep -e '= !DICompileUnit' -l -- test | grep -v test/Bitcode | xargs sed -i '' -e 's,= !DICompileUnit,= distinct !DICompileUnit,' I imagine something similar should work for out-of-tree testcases. llvm-svn: 243885
* AVX512: Add encoding tests to vptestnm instructionsIgor Breger2015-07-282-0/+465
| | | | | | Differential Revision: http://reviews.llvm.org/D11521 llvm-svn: 243391
* AVX512: Implemented encoding and intrinsics for VGETEXPSS/D instructionsIgor Breger2015-07-281-0/+80
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11528 llvm-svn: 243390
* Implemented encoding and intrinsics of the following instructionsIgor Breger2015-07-264-0/+2064
| | | | | | | | | | vunpckhps/pd, vunpcklps/pd, vpunpcklbw, vpunpckhbw, vpunpcklwd, vpunpckhwd, vpunpckldq, vpunpckhdq, vpunpcklqdq, vpunpckhqdq Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11509 llvm-svn: 243246
* AVX-512: Implemented encoding , DAG lowering and intrinsics for Integer ↵Igor Breger2015-07-243-0/+1800
| | | | | | | | | | Truncate with/without saturation Added tests for DAG lowering ,encoding and intrinsic Differential Revision: http://reviews.llvm.org/D11218 llvm-svn: 243122
* [X86] Fix order of operands for ins and outs instructions when parsing intel ↵Michael Kuperstein2015-07-231-0/+14
| | | | | | | | | syntax Patch by: marina.yatsina@intel.com Differential Revision: http://reviews.llvm.org/D11337 llvm-svn: 243001
* Revert r242990: "AVX-512: Implemented encoding , DAG lowering and ..."Chandler Carruth2015-07-233-1800/+0
| | | | | | | | | | This commit broke the build. Numerous build bots broken, and it was blocking my progress so reverting. It should be trivial to reproduce -- enable the BPF backend and it should fail when running llvm-tblgen. llvm-svn: 242992
* AVX-512: Implemented encoding , DAG lowering and intrinsics for Integer ↵Igor Breger2015-07-233-0/+1800
| | | | | | | | | | Truncate with/without saturation Added tests for DAG lowering ,encoding and intrinsic Differential Revision: http://reviews.llvm.org/D11218 llvm-svn: 242990
* [X86][AVX512] add reduce/range/scalef/rndScaleAsaf Badouh2015-07-224-0/+1520
| | | | | | | | include encoding and intrinsics Differential Revision: http://reviews.llvm.org/D11222 llvm-svn: 242896
* Fix test from r242886 to use the right triple.Michael Kuperstein2015-07-221-0/+1
| | | | llvm-svn: 242889
* [X86] Add .intel_syntax noprefix directive to intel-syntax x86 asm outputMichael Kuperstein2015-07-221-0/+9
| | | | | | | Patch by: michael.zuckerman@intel.com Differential Revision: http://reviews.llvm.org/D11223 llvm-svn: 242886
* AVX512 : Implemented VPMADDUBSW and VPMADDWD instruction , Igor Breger2015-07-212-0/+360
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11351 llvm-svn: 242761
* [X86] Add support for tbyte memory operand size for Intel-syntax x86 assemblyMichael Kuperstein2015-07-191-0/+2
| | | | | | | Differential Revision: http://reviews.llvm.org/D11257 Patch by: marina.yatsina@intel.com llvm-svn: 242639
* AVX-512: Added all AVX-512 forms of Vector Convert for Float/Double/Int/Long ↵Elena Demikhovsky2015-07-134-0/+2665
| | | | | | | | | | | | types. In this patch I have only encoding. Intrinsics and DAG lowering will be in the next patch. I temporary removed the old intrinsics test (just to split this patch). Half types are not covered here. Differential Revision: http://reviews.llvm.org/D11134 llvm-svn: 242023
* [llvm-objdump] Require that jump targets shown in -d are functionsDavid Majnemer2015-07-091-0/+4
| | | | | | | Don't let the disassembler pick call <.text> if a function happens to live at the start of the section by only using function symbols. llvm-svn: 241830
* [llvm-objdump] Print the call target next to the instructionDavid Majnemer2015-07-071-11/+11
| | | | | | | GNU binutils provides this behavior. objdump -r doesn't really help when you aren't dealing with relocation object files. llvm-svn: 241631
* [X86][AVX512] Multiply Packed Unsigned Integers with Round and ScaleAsaf Badouh2015-07-062-0/+109
| | | | | | | | | pmulhrsw review: http://reviews.llvm.org/D10948 llvm-svn: 241443
* [x86][AVX512] add Multiply High OpAsaf Badouh2015-07-052-0/+216
| | | | | | | | | include encoding and intrinsics tests. review http://reviews.llvm.org/D10896 llvm-svn: 241406
* [X86] Add proper 64-bit mode checks to jrcxz and jcxz.Craig Topper2015-07-041-0/+6
| | | | llvm-svn: 241381
* AVX-512: Implemented missing encoding for FMA scalar instructionsIgor Breger2015-07-011-0/+1249
| | | | | | | | Added tests for encoding Differential Revision: http://reviews.llvm.org/D10865 llvm-svn: 241159
* AVX-512: all forms of SCATTER instruction on SKX,Elena Demikhovsky2015-06-291-0/+128
| | | | | | encoding, intrinsics and tests. llvm-svn: 240936
* AVX-512: Implemented missing encoding and intrinsics for FMA instructionsIgor Breger2015-06-292-0/+6697
| | | | | | | | Added tests for DAG lowering ,encoding and intrinsics Differential Revision: http://reviews.llvm.org/D10796 llvm-svn: 240926
* [x86][AVX512]Asaf Badouh2015-06-282-0/+367
| | | | | | | | | | | Add vscalef support include encoding and intrinsics review: http://reviews.llvm.org/D10730 llvm-svn: 240906
* AVX-512: Added all SKX forms of GATHER instructions.Elena Demikhovsky2015-06-282-0/+303
| | | | | | | Added intrinsics. Added encoding and tests. llvm-svn: 240905
* [MC] Ensure that pending labels are flushed when -mc-relax-all flag is usedPetr Hosek2015-06-271-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The current implementation doesn't always flush all pending labels beforeemitting data which can result in an incorrectly placed labels in case when when instruction bundling is enabled and -mc-relax-all flag is being used. To address this issue, we always flush pending labels before emitting data. The change was tested by running PNaCl toolchain trybots with -mc-relax-all flag set. Fixes https://code.google.com/p/nativeclient/issues/detail?id=4063 Test Plan: Regression test attached Reviewers: mseaborn Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D10325 llvm-svn: 240870
* [MC] Align fragments when -mc-relax-all flag is usedPetr Hosek2015-06-272-0/+54
| | | | | | | | | | | | | | | | | | | | | | | Summary: Ensure that fragments are bundle aligned when instruction bundling is enabled and the -mc-relax-all flag is set. This is implicitly assumed by the bundle padding implementation but this assumption does not hold when custom alignment is being used. The change was tested by running PNaCl toolchain trybots with -mc-relax-all flag set. Fixes https://code.google.com/p/nativeclient/issues/detail?id=4063 Test Plan: Regression test attached Reviewers: mseaborn Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D10044 llvm-svn: 240869
* Add a test for a recent regression.Rafael Espindola2015-06-251-0/+13
| | | | llvm-svn: 240656
* AVX-512: Added all forms of VPABS instructionElena Demikhovsky2015-06-233-0/+409
| | | | | | Added all intrinsics, tests for encoding, tests for intrinsics. llvm-svn: 240386
* [FaultMaps] Add a parser for the __llvm__faultmaps section.Sanjoy Das2015-06-221-0/+29
| | | | | | | | | | | | | | | Summary: The parser is exercised by llvm-objdump using -print-fault-maps. As is probably obvious, the code itself was "heavily inspired" by http://reviews.llvm.org/D10434. Reviewers: reames, atrick, JosephTremoulet Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10491 llvm-svn: 240304
* AVX-512: added VPSHUFB instruction - all SKX formsElena Demikhovsky2015-06-222-0/+108
| | | | | | Added intrinsics and encoding tests. llvm-svn: 240277
* AVX-512: All forms of VCOPMRESS VEXPAND instructions,Elena Demikhovsky2015-06-222-0/+503
| | | | | | encoding tests. llvm-svn: 240272
* [AVX512]Asaf Badouh2015-06-182-0/+576
| | | | | | | | | | add instructions: VPAVGB and VPAVGW review http://reviews.llvm.org/D10504 llvm-svn: 240012
* AVX-512: (fixed) Added encoding of all forms of VPERMT2W/D/Q/PS/PD and ↵Elena Demikhovsky2015-06-184-16/+1336
| | | | | | | | VPERMI2W/D/Q/PS/PD. Intrinsics and tests for them are comming in the next patch. llvm-svn: 240003
* reverted 239999 due to test failuresElena Demikhovsky2015-06-184-1336/+16
| | | | llvm-svn: 240001
* AVX-512: Added encoding of all forms of VPERMT2W/D/Q/PS/PDElena Demikhovsky2015-06-184-16/+1336
| | | | | | | and VPERMI2W/D/Q/PS/PD. Intrinsics and tests for them are comming in the next patch. llvm-svn: 239999
* Add support for parsing the XOR operator in Intel syntax inline assembly.Michael Kuperstein2015-06-141-0/+2
| | | | | | | Differential Revision: http://reviews.llvm.org/D10385 Patch by marina.yatsina@intel.com llvm-svn: 239695
* AVX-512: Implemented cvtsi2ss/d cvtusi2ss/d instructions with round control ↵Igor Breger2015-06-141-0/+492
| | | | | | | | | | | for KNL. Added intrinsics for cvtsi2ss/d instructions. Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D10430 llvm-svn: 239694
* X86-MPX: Implemented encoding for MPX instructions.Elena Demikhovsky2015-06-091-0/+38
| | | | | | Added encoding tests. llvm-svn: 239403
* AVX-512: Implemented 256/128bit VALIGND/Q instructions for SKX and KNLIgor Breger2015-06-082-0/+179
| | | | | | | | | Implemented DAG lowering for all these forms. Added tests for DAG lowering and encoding. Differential Revision: http://reviews.llvm.org/D10310 llvm-svn: 239300
* [objdump] Moving PrintImmHex out of MachODump and in to llvm-objdump and ↵Colin LeMahieu2015-06-071-0/+10
| | | | | | setting instprinter appropriately. llvm-svn: 239265
* Test commitIgor Breger2015-06-041-0/+1
| | | | llvm-svn: 239019
* AVX-512: added all SKX forms of VPERMW/D/Q instructions.Elena Demikhovsky2015-06-042-0/+379
| | | | | | | Added all forms of VPERMPS/PD instrcuctions. Added encoding tests. llvm-svn: 239016
* re-apply 238809Asaf Badouh2015-06-032-0/+376
| | | | | | | | | | AVX-512: Implemented GETEXP instruction for KNL and SKX Added rounding mode modifier for SQRTPS/PD Added tests for encoding and intrinsics. CR: http://reviews.llvm.org/D9991 llvm-svn: 238923
* AVX-512: Implemented SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2 instructions ↵Elena Demikhovsky2015-06-032-0/+480
| | | | | | | | | | for SKX and KNL. Added tests for encoding. By Igor Breger (igor.breger@intel.com) llvm-svn: 238917
* AVX-512: Implemented VRANGESD and VRANGESS instructions for SKX Implemented ↵Elena Demikhovsky2015-06-021-0/+96
| | | | | | | | | | DAG lowering for all these forms. Added tests for encoding. By Igor Breger (igor.breger@intel.com) llvm-svn: 238834
* AVX-512: Implemented VFIXUPIMMSD and VFIXUPIMMSS instructions for KNLElena Demikhovsky2015-06-022-0/+179
| | | | | | | | | Implemented DAG lowering for all these forms. Added tests for encoding. By Igor Breger (igor.breger@intel.com) llvm-svn: 238811
* revert 238809Asaf Badouh2015-06-022-375/+0
| | | | llvm-svn: 238810
OpenPOWER on IntegriCloud