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* AVX512: Implemented encoding for the follow instructions.Igor Breger2015-11-194-0/+1440
| | | | | | | | vmovapd.s, vmovaps.s, vmovdqa32.s, vmovdqa64.s, vmovdqu16.s, vmovdqu32.s, vmovdqu64.s, vmovdqu8.s, vmovupd.s, vmovups.s Differential Revision: http://reviews.llvm.org/D14768 llvm-svn: 253546
* AVX512: Implemented encoding for vpextrw.s instruction.Igor Breger2015-11-181-0/+48
| | | | | | Differential Revision: http://reviews.llvm.org/D14766 llvm-svn: 253447
* AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP ↵Igor Breger2015-11-162-0/+217
| | | | | | | | instructions. Differential Revision: http://reviews.llvm.org/D14322 llvm-svn: 253185
* Revert r253160.Igor Breger2015-11-152-217/+0
| | | | | | It broke layering violation. Reproducible with BUILD_SHARED_LIBS=ON. llvm-svn: 253163
* AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP ↵Igor Breger2015-11-152-0/+217
| | | | | | | | instructions. Differential Revision: http://reviews.llvm.org/D14322 llvm-svn: 253160
* [x86] translating "fp" (floating point) instructions from ↵Michael Zuckerman2015-11-122-0/+28
| | | | | | | | | | | {fadd,fdiv,fmul,fsub,fsubr,fdivr} to {faddp,fdivp,fmulp,fsubp,fsubrp,fdivrp} LLVM Missing the following instructions: fadd\fdiv\fmul\fsub\fsubr\fdivr. GAS and MS supporting this instruction and lowering them in to a faddp\fdivp\fmulp\fsubp\fsubrp\fdivrp instructions. Differential Revision: http://reviews.llvm.org/D14217 llvm-svn: 252908
* Visibly fail if attempting to encode register AH,BH,CH,DH in a REX-prefixed ↵Douglas Katzman2015-11-111-0/+3
| | | | | | | | | instruction. Differential Revision: http://reviews.llvm.org/D13316 Fixes PR25003 llvm-svn: 252743
* AVX512 : Implemented encoding and DAG lowering for VMOVHPS/PD and VMOVLPS/PD ↵Igor Breger2015-11-101-0/+192
| | | | | | | | instructions. Differential Revision: http://reviews.llvm.org/D14492 llvm-svn: 252592
* revert rev. 252153 due to build failure on ubuntuAsaf Badouh2015-11-051-127/+0
| | | | | | [X86][AVX512] add comi with Sae llvm-svn: 252154
* [X86][AVX512] add comi with SaeAsaf Badouh2015-11-051-0/+127
| | | | | | | | add builtin_ia32_vcomisd and builtin_ia32_vcomisd Differential Revision: http://reviews.llvm.org/D14331 llvm-svn: 252153
* [X86][AVX512] small bugfix in VPBROADCASTMAsaf Badouh2015-11-051-0/+15
| | | | | | | | VPBROADCASTMW2D and VPBROADCASTMB2Q Differential Revision: http://reviews.llvm.org/D14335 llvm-svn: 252151
* Fix pr24832.Rafael Espindola2015-11-051-0/+14
| | | | | | It is pretty simple now that the yak is shaved. llvm-svn: 252105
* AVX512: add encoding tests for vmovq/d instructions.Igor Breger2015-11-031-1/+346
| | | | llvm-svn: 251903
* AVX512: Implemented encoding and intrinsics for VBROADCASTI32x2 and ↵Igor Breger2015-11-022-0/+362
| | | | | | | | VBROADCASTF32x2 instructions. Differential Revision: http://reviews.llvm.org/D14216 llvm-svn: 251781
* [X86][AVX512] [X86][AVX512] add convert float to halfAsaf Badouh2015-10-272-0/+152
| | | | | | | | convert float to half with mask/maskz for the reg to reg version and mask for the reg to mem version (there is no maskz version for reg to mem). Differential Revision: http://reviews.llvm.org/D14113 llvm-svn: 251409
* [MC] Add support for GNU as-compatible binary operator precedenceDavid Majnemer2015-10-261-1/+1
| | | | | | | | | | GNU as and Darwin give the various binary operators different precedence. LLVM's MC supported the Darwin semantics but not the GNU semantics. This fixes PR25311. llvm-svn: 251271
* [X86][AVX512] extend vcvtph2ps to support xmm/ymm and sae versionsAsaf Badouh2015-10-222-0/+110
| | | | | | Differential Revision: http://reviews.llvm.org/D13945 llvm-svn: 251018
* [X86] Add AMD mwaitx, monitorx, and clzero instructions to the assembly ↵Craig Topper2015-10-212-0/+36
| | | | | | parser and disassembler. llvm-svn: 250911
* AVX512: Implemented encoding and intrinsics for VPBROADCASTB/W/D/Q instructions.Igor Breger2015-10-204-0/+853
| | | | | | Differential Revision: http://reviews.llvm.org/D13884 llvm-svn: 250819
* [X86][AVX512DQ] add scalar fpclassAsaf Badouh2015-10-181-0/+144
| | | | | | Differential Revision: http://reviews.llvm.org/D13769 llvm-svn: 250650
* AVX512: Implemented encoding and intrinsics for vpternlogd/q.Igor Breger2015-10-152-0/+362
| | | | | | Differential Revision: http://reviews.llvm.org/D13768 llvm-svn: 250396
* [X86] Change the immediate for IN/OUT instructions to u8imm so the assembly ↵Craig Topper2015-10-121-0/+10
| | | | | | parser will check the size. llvm-svn: 250012
* [X86] Remove special validation for INT immediate operand from AsmParser. ↵Craig Topper2015-10-112-2/+13
| | | | | | | | Instead mark its operand type as u8imm which will cause it to fail to match. This is more consistent with other instruction behavior. This also fixes a bug where negative immediates below -128 were not being reported as errors. llvm-svn: 249989
* AVX512: vpextrb/w/d/q and vpinsrb/w/d/q implementation.Igor Breger2015-10-082-0/+503
| | | | | | | | | This instructions doesn't have intrincis. Added tests for lowering and encoding. Differential Revision: http://reviews.llvm.org/D12317 llvm-svn: 249688
* AVX512: Change encoding of vpshuflw and vpshufhw instructions. Implement WIG ↵Igor Breger2015-10-072-120/+361
| | | | | | | | | | as W0 and not W1, like all other instruction have been implemented. Add encoding tests. Differential Revision: http://reviews.llvm.org/D13471 llvm-svn: 249521
* AVX512: Implemented encoding and intrinsics for VPERMILPS/PD instructions.Igor Breger2015-10-042-0/+696
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D12690 llvm-svn: 249261
* [X86][AVX512] add masked version for RSQRT14 & RCP14 Scalar FPAsaf Badouh2015-09-211-0/+143
| | | | | | Differential Revision: http://reviews.llvm.org/D12524 llvm-svn: 248147
* AVX512: Implemented encoding and intrinsics for vcmpss/sd.Igor Breger2015-09-201-0/+88
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D12593 llvm-svn: 248121
* [X86][AVX512] extend support in Scalar conversionAsaf Badouh2015-09-204-0/+2073
| | | | | | | | | | add scalar FP to Int conversion with truncation intrinsics add scalar conversion FP32 from/to FP64 intrinsics add rounding mode and SAE mode encoding for these intrinsics Differential Revision: http://reviews.llvm.org/D12665 llvm-svn: 248117
* AVX512: vsqrtss/sd encoding and intrinsics implementation.Igor Breger2015-09-201-0/+104
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D12102 llvm-svn: 248116
* [X86][AVX512DQ] Add fpclass instruction Asaf Badouh2015-09-202-0/+672
| | | | | | Differential Revision: http://reviews.llvm.org/D12931 llvm-svn: 248115
* AVX512: Implement instructions encoding, lowering and intrinsicsIgor Breger2015-09-204-0/+720
| | | | | | | | | vinserti64x4, vinserti64x2, vinserti32x8, vinserti32x4, vinsertf64x4, vinsertf64x2, vinsertf32x8, vinsertf32x4 Added tests for encoding, lowering and intrinsics. Differential Revision: http://reviews.llvm.org/D11893 llvm-svn: 248111
* AVX512: Implemented encoding and intrinsics forIgor Breger2015-09-104-0/+864
| | | | | | | | | vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4 Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11802 llvm-svn: 247276
* Revert "AVX512: Implemented encoding and intrinsics for vextracti64x4 ↵Renato Golin2015-09-094-864/+0
| | | | | | | | ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4 Added tests for intrinsics and encoding." This reverts commit r247149, as it was breaking numerous buildbots of varied architectures. llvm-svn: 247177
* AVX512: Implemented encoding and intrinsics forIgor Breger2015-09-094-0/+864
| | | | | | | | | vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4 Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11802 llvm-svn: 247149
* AVX512: kunpck encoding implementation Igor Breger2015-09-082-0/+12
| | | | | | | | Added tests for encoding. Differential Revision: http://reviews.llvm.org/D12061 llvm-svn: 247010
* AVX512: Implemented encoding and intrinsics for vplzcntq, vplzcntd, ↵Igor Breger2015-09-032-0/+1348
| | | | | | | | | | vpconflictq, vpconflictd Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11931 llvm-svn: 246750
* [X86][AVX512VLBW] add support in byte shift and SADAsaf Badouh2015-09-022-0/+459
| | | | | | | | | add byte shift left/right add SAD - compute sum of absolute differences Differential Revision: http://reviews.llvm.org/D12479 llvm-svn: 246654
* AVX512: Implemented encoding and intrinsics for VGETMANTPD/S , VGETMANTSD/S ↵Igor Breger2015-09-022-0/+472
| | | | | | | | | | instructions Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11593 llvm-svn: 246642
* AVX512: Implemented encoding and intrinsics for vshufps/d.Igor Breger2015-09-022-0/+360
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11709 llvm-svn: 246640
* AVX512: ktest implemantationIgor Breger2015-08-313-0/+44
| | | | | | | | Added tests for encoding. Differential Revision: http://reviews.llvm.org/D11979 llvm-svn: 246439
* AVX512: Implemented encoding and intrinsics for vdbpsadbwIgor Breger2015-08-312-0/+199
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D12491 llvm-svn: 246436
* AVX512: kadd implementationIgor Breger2015-08-312-0/+24
| | | | | | | | Added tests for encoding. Differential Revision: http://reviews.llvm.org/D11973 llvm-svn: 246432
* AVX512: Add encoding tests for vscatter instructionsIgor Breger2015-08-312-0/+192
| | | | | | Differential Revision: http://reviews.llvm.org/D11941 llvm-svn: 246431
* AVX512: Implemented encoding and intrinsics for vpalignrIgor Breger2015-08-312-0/+200
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D12270 llvm-svn: 246428
* [X86] Add support for mmword memory operand size for Intel-syntax x86 assemblyMichael Zuckerman2015-08-241-0/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D12151 llvm-svn: 245835
* Fix symbol value computation when part of the expression is weak.Rafael Espindola2015-08-201-1/+6
| | | | | | | This matches the behaviour of the gnu assembler and is part of fixing pr24486. llvm-svn: 245576
* [X86] Fix FBLD and FBSTPMarina Yatsina2015-08-201-0/+5
| | | | | | | | | | FBLD and FBSTP should receive TBYTE because it is defined as FBLD m80 FBSTP m80 Differential Revision: http://reviews.llvm.org/D11748 llvm-svn: 245553
* [X86] Fix bug in COMISD and COMISS definition in td filesMarina Yatsina2015-08-202-0/+18
| | | | | | | | | | | | COMISD should receive QWORD because it is defined as (V)COMISD xmm1, xmm2/m64 COMISS should receive DWORD because it is defined as (V)COMISS xmm1, xmm2/m32 Differential Revision: http://reviews.llvm.org/D11712 llvm-svn: 245551
* [MC] Convert the last test using macho-dump under X86/ to llvm-readobj.Davide Italiano2015-08-121-4/+20
| | | | llvm-svn: 244732
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