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* The fix for PR22004: X86AsmParser.cpp asserts: OperandStack.size() > 1 && ↵Andrew V. Tischenko2017-05-261-0/+3
| | | | | | "Too few operands." llvm-svn: 303985
* [X86] Adding vpopcntd and vpopcntq instructionsOren Ben Simhon2017-05-251-0/+225
| | | | | | | | | AVX512_VPOPCNTDQ is a new feature set that was published by Intel. The patch represents the LLVM side of the addition of two new intrinsic based instructions (vpopcntd and vpopcntq). Differential Revision: https://reviews.llvm.org/D33169 llvm-svn: 303858
* [X86][LWP] Add llvm support for LWP instructions (reapplied).Simon Pilgrim2017-05-032-0/+57
| | | | | | | | | | This patch adds support for the the LightWeight Profiling (LWP) instructions which are available on all AMD Bulldozer class CPUs (bdver1 to bdver4). Reapplied - this time without changing line endings of existing files. Differential Revision: https://reviews.llvm.org/D32769 llvm-svn: 302041
* Revert rL302028 due to accidental line ending changes.Simon Pilgrim2017-05-032-57/+0
| | | | llvm-svn: 302038
* [X86][LWP] Add llvm support for LWP instructions.Simon Pilgrim2017-05-032-0/+57
| | | | | | | | This patch adds support for the the LightWeight Profiling (LWP) instructions which are available on all AMD Bulldozer class CPUs (bdver1 to bdver4). Differential Revision: https://reviews.llvm.org/D32769 llvm-svn: 302028
* 2 tests that were lost in rL301390Andrew V. Tischenko2017-04-271-0/+7
| | | | llvm-svn: 301529
* [X86][SSE2] Fix asm string for movq (Move Quadword) instruction.Ayman Musa2017-04-261-10/+6
| | | | | | | | Replace "mov{d|q}" with "movq". Differential Revision: https://reviews.llvm.org/D32220 llvm-svn: 301386
* [X86][MS-compatability]Allow named synonymous for MS-assembly operatorsCoby Tayree2017-04-041-7/+41
| | | | | | | | | | This patch enhances X86AsmParser's immediate expression parsing abilities, to include a named synonymous for selected binary/unary bitwise operators: {and,shl,shr,or,xor,not}, ultimately achieving better MS-compatability MASM reference: https://msdn.microsoft.com/en-us/library/94b6khh4.aspx Differential Revision: D31277 llvm-svn: 299439
* Check that line table entries don't spill over between sections even if ↵David Blaikie2017-03-161-0/+15
| | | | | | they're empty at the end of a section llvm-svn: 297922
* [X86] Clzero intrinsic and its addition under znver1Craig Topper2017-02-092-0/+16
| | | | | | | | | | | | | | | | | This patch does the following. 1. Adds an Intrinsic int_x86_clzero which works with __builtin_ia32_clzero 2. Identifies clzero feature using cpuid info. (Function:8000_0008, Checks if EBX[0]=1) 3. Adds the clzero feature under znver1 architecture. 4. The custom inserter is added in Lowering. 5. A testcase is added to check the intrinsic. 6. The clzero instruction is added to assembler test. Patch by Ganesh Gopalasubramanian with a couple formatting tweaks, a disassembler test, and using update_llc_test.py from me. Differential revision: https://reviews.llvm.org/D29385 llvm-svn: 294558
* [X86] Remove PCOMMIT instruction support since Intel has deprecated this ↵Craig Topper2017-02-081-4/+0
| | | | | | | | instruction with no plans to release products with it. Intel's documentation for the deprecation https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction llvm-svn: 294405
* [X86] Fix printing of sha256rnds2 to include the implicit %xmm0 argument.Craig Topper2017-02-051-4/+4
| | | | llvm-svn: 294132
* [X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit ↵Craig Topper2017-02-051-14/+14
| | | | | | %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
* MC: Introduce the ABS8 symbol modifier.Peter Collingbourne2017-01-311-0/+8
| | | | | | | | | | | @ABS8 can be applied to symbols which appear as immediate operands to instructions that have a 8-bit immediate form for that operand. It causes the assembler to use the 8-bit form and an 8-bit relocation (e.g. R_386_8 or R_X86_64_8) for the symbol. Differential Revision: https://reviews.llvm.org/D28688 llvm-svn: 293667
* Fix line endings.Eli Friedman2017-01-301-10779/+10779
| | | | llvm-svn: 293554
* [X86][Disassembler] Added SALC instructionChris Ray2017-01-291-0/+4
| | | | | | | | | | | | Reviewers: joe.abbey, craig.topper Reviewed By: craig.topper Subscribers: majnemer, llvm-commits Differential Revision: https://reviews.llvm.org/D29201 llvm-svn: 293447
* [X86] Adding FFREEP instruction.Chris Ray2017-01-271-10771/+10775
| | | | | | | | | | | | | | Summary: Small change to get the FREEP instruction to decode properly. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29193 llvm-svn: 293314
* [X86]Enable the use of 'mov' with a 64bit GPR and a large immediateCoby Tayree2017-01-251-0/+2
| | | | | | | | | | | Enable the next form (intel style): "mov <reg64>, <largeImm>" which is should be available, where <largeImm> stands for immediates which exceed the range of a singed 32bit integer Differential Revision: https://reviews.llvm.org/D28988 llvm-svn: 293030
* [X86] Fix for bugzilla 31576 - add support for "data32" instruction prefixMarina Yatsina2017-01-187-0/+78
| | | | | | | | | | | This patch fixes bugzilla 31576 (https://llvm.org/bugs/show_bug.cgi?id=31576). "data32" instruction prefix was not defined in the llvm. An exception had to be added to the X86 tablegen and AsmPrinter because both "data16" and "data32" are encoded to 0x66 (but in different modes). Differential Revision: https://reviews.llvm.org/D28468 llvm-svn: 292352
* [AVX-512] Add more gather/scatter encoding test cases.Craig Topper2017-01-162-0/+176
| | | | llvm-svn: 292089
* [AVX-512] Correct memory operand size for VPGATHERQPS and VPGATHERQDCraig Topper2017-01-161-56/+56
| | | | | | | | | with ZMM index. Similar for SCATTER and the prefetch gather and scatter instructions. Fixes PR31618. llvm-svn: 292088
* [X86][AVX2] Passing the appropriate memory operand class to VPMADDWD ↵Ayman Musa2016-12-222-0/+114
| | | | | | | | | | instruction. Replacing the memory operand in the ymm version of VPMADDWD from i128mem to i256mem. Differential Revision: https://reviews.llvm.org/D28024 llvm-svn: 290333
* [X86] [AVX512] Minor fix in encoding of scalar EVEX instructions. NFC.Michael Zuckerman2016-12-182-36/+36
| | | | | | | | | | | | Commit on behalf of Gadi Haber Removed EVEX_V512 prefix from scalar EVEX instructions since HW ignores L'L bits anyway (LIG). 4 instructions are modified. The changed encodings are validated with XED. Rviewers: delena, igorb Differential revision: https://reviews.llvm.org/D27802 llvm-svn: 290065
* [LMT] Restrict nop length to oneAsaf Badouh2016-12-011-3/+22
| | | | | | | | | not all lakemont MCU support long nop. we can't assume we can generate long nop by default for MCU. Differential Revision: https://reviews.llvm.org/D26895 llvm-svn: 288363
* small fixup which enables the issuing of the aforementioned instruction (w/o ↵Coby Tayree2016-11-211-0/+2
| | | | | | | | operands), on MS/Intel syntax. Differential Revision: https://reviews.llvm.org/D26913 llvm-svn: 287548
* The 'vpmultishiftqb' instruction was implemented falsely, this patch amend it.Coby Tayree2016-11-201-0/+37
| | | | | | | | More specifically - (MS dialect) broadcasting variants were implemented falsely. Differential Revision: https://reviews.llvm.org/D26257 llvm-svn: 287501
* Some instructions were missing, other implemented falsely. this patch aims ↵Coby Tayree2016-11-202-0/+127
| | | | | | | | | | | | | | | | | | | | at amending those issues. full list: vcvtps2pd vcvtudq2pd vcvtps2qq vcvttps2qq vcvtps2uqq vcvttps2uqq variants are: [Dst]XMM(zero-masked/merge-masked/unmasked) [Src]Mem64 Differential Revision: https://reviews.llvm.org/D26799 llvm-svn: 287500
* [AVX-512] Add suffixless aliases for EVEX encoded ↵Craig Topper2016-11-141-0/+18
| | | | | | | | vcvtsi2ss/vcvtsi2sd/vcvtusi2ss/vcvtusi2sd. This matches the VEX behavior. Fixes another problem from PR28850. llvm-svn: 286790
* [X86] Cleanup 'x' and 'y' mnemonic suffixes for ↵Craig Topper2016-11-144-14/+333
| | | | | | | | | | | | | vcvtpd2dq/vcvttpd2dq/vcvtpd2ps and similar instructions. -Don't print the 'x' suffix for the 128-bit reg/mem VEX encoded instructions in Intel syntax. This is consistent with the EVEX versions. -Don't print the 'y' suffix for the 256-bit reg/reg VEX encoded instructions in Intel or AT&T syntax. This is consistent with the EVEX versions. -Allow the 'x' and 'y' suffixes to be used for the reg/mem forms when we're assembling using Intel syntax. -Allow the 'x' and 'y' suffixes on the reg/reg EVEX encoded instructions in Intel or AT&T syntax. This is consistent with what VEX was already allowing. This should fix at least some of PR28850. llvm-svn: 286787
* X86: Allow expressions to appear as u8imm operands.Peter Collingbourne2016-10-201-0/+7
| | | | llvm-svn: 284688
* [x86][inline-asm][avx512] allow swapping of '{k<num>}' & '{z}' marksMichael Zuckerman2016-10-182-0/+8
| | | | | | | | | | | | | | | | | | | | | | | Committing on behalf of Coby Tayree: After check-all and LGTM Desc: AVX512 allows dest operand to be followed by an op-mask register specifier ('{k<num>}', which in turn may be followed by a merging/zeroing specifier ('{z}') Currently, the following forms are allowed: {k<num>} {k<num>}{z} This patch allows the following forms: {z}{k<num>} and ignores the next form: {z} Justification would be quite simple - GCC Differential Revision: http://reviews.llvm.org/D25013 llvm-svn: 284479
* [X86] Fix intel syntax push parsing bugNirav Dave2016-10-061-0/+23
| | | | | | | | | | | | | | | Change erroneous parsing of push immediate instructions in intel syntax to default to pointer size by rewriting into the ATT style for matching. This fixes PR22028. Reviewers: majnemer, rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25288 llvm-svn: 283457
* [X86] Don't randomly encode %rip where illegalDouglas Katzman2016-10-052-0/+13
| | | | | | Differential Revision: https://reviews.llvm.org/D25112 llvm-svn: 283326
* [X86] Fix some tests that didn't assert anythingDouglas Katzman2016-10-051-3/+3
| | | | llvm-svn: 283322
* [x86] Accept 'retn' as an alias to 'ret[lqw]'\'ret' (At&t\Intel)Marina Yatsina2016-09-281-0/+16
| | | | | | | | | | Implement 'retn' simply by aliasing it to the relevant 'ret' instruction Commit on behalf of coby Differential Revision: https://reviews.llvm.org/D24346 llvm-svn: 282601
* Add support for Code16GCCNirav Dave2016-09-261-0/+67
| | | | | | | | | | | | | [X86] The .code16gcc directive parses X86 assembly input in 32-bit mode and outputs in 16-bit mode. Teach parser to switch modes appropriately. Reviewers: dwmw2, craig.topper Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D20109 llvm-svn: 282430
* X86: loosen an overly aggressive MachO assertionSaleem Abdulrasool2016-09-201-0/+11
| | | | | | | | | | | | | We would assert that the FP setup CFI used esp/rsp always. This held up in practice when the code was generated from IR. However, with the integrated assembler, it is possible to have the input be user specified assembly. In such a case, we cannot assume that the function implementation has a compact unwind representation. Loosen the assertion into a check and bail if we cannot represent the frame pointer in the compact unwinding. Addresses PR30453! llvm-svn: 281986
* [X86] Don't allow DR8-DR15 to be assembled in 32-bit mode. Add missing test ↵Craig Topper2016-08-271-0/+6
| | | | | | for CR8-CR15. llvm-svn: 279921
* [X86] Improve code size on X86 segment movesNirav Dave2016-08-082-2/+26
| | | | | | | | | | | | | | Moves of a value to a segment register from a 16-bit register is equivalent to one from it's corresponding 32-bit register. Match gas's behavior and rewrite instructions to the shorter of equivalent forms. Reviewers: rnk, ab Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23166 llvm-svn: 278031
* [AVX512] Add aliases for vcvttss2si{l|q}, vcvttsd2si{l|q}, vcvttss2usi{l|q}, ↵Igor Breger2016-08-031-0/+128
| | | | | | | | vcvttsd2usi{l|q} instructions. Differential Revision: http://reviews.llvm.org/D23111 llvm-svn: 277586
* [MC] Fix Intel Operand assembly parsing for .set idsNirav Dave2016-08-022-0/+18
| | | | | | | | | | | | | | | | | Recommitting after fixing overaggressive fastpath return in parsing. Fix intel syntax special case identifier operands that refer to a constant (e.g. .set <ID> n) to be interpreted as immediate not memory in parsing. Associated commit to fix clang test commited shortly. Reviewers: rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22585 llvm-svn: 277489
* Revert r276895 "[MC][X86] Fix Intel Operand assembly parsing for .set ids"Hans Wennborg2016-08-012-18/+0
| | | | | | This caused PR28805. Adding a regression test. llvm-svn: 277402
* [MC][X86] Fix Intel Operand assembly parsing for .set idsNirav Dave2016-07-272-0/+18
| | | | | | | | | | | | | Fix intel syntax special case identifier operands that refer to a constant (e.g. .set <ID> n) to be interpreted as immediate not memory in parsing. Reviewers: rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22585 llvm-svn: 276895
* [MC] Don't crash when trying to emit a relocation against .bss.Davide Italiano2016-07-261-0/+9
| | | | | | Turn that into an error instead. llvm-svn: 276783
* [X86][MC] Fix bracket expression parsing in intel-style assembly.Nirav Dave2016-07-141-0/+5
| | | | | | | | | | | | | | Only perform struct field check on Identifier tokens. Fixes PR28547. Reviewers: rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22361 llvm-svn: 275445
* [X86] Decode MPX BND registers.Ahmed Bougacha2016-07-141-11/+14
| | | | | | | | | | | | | We were able to assemble, but not disassemble. Note that fixupRMValue was truncating EA_REG_BND0-3 because we hit the uint8_t max. The control registers were already squarely above it, but I don't think they ever go in .r/m, only in .reg. I also did notice an extra REX.W in our encoding, but I think that's fine. llvm-svn: 275427
* Fix branch relaxation in 16-bit mode.Nirav Dave2016-07-111-0/+31
| | | | | | | | | | | | | | | Thread through MCSubtargetInfo to relaxInstruction function allowing relaxation to generate jumps with 16-bit sized immediates in 16-bit mode. This fixes PR22097. Reviewers: dwmw2, tstellarAMD, craig.topper, jyknight Subscribers: jfb, arsenm, jyknight, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D20830 llvm-svn: 275068
* Permit memory operands in ins/outs instructionsNirav Dave2016-06-292-0/+70
| | | | | | | | | | | | | | | [x86] (PR15455) While (ins|outs)[bwld] instructions do not take %dx as a memory operand, various unofficial references do and objdump disassembles to this format. Extend special treatment of similar (in|out)[bwld] operations. Reviewers: craig.topper, rnk, ab Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D18837 llvm-svn: 274152
* [x86] avoid printing unnecessary sign bits of hex immediates in asm comments ↵Sanjay Patel2016-05-281-2/+2
| | | | | | | | | | | (PR20347) It would be better to check the valid/expected size of the immediate operand, but this is generally better than what we print right now. Differential Revision: http://reviews.llvm.org/D20385 llvm-svn: 271114
* [MCExpr] avoid UB via negation of INT_MINSanjay Patel2016-05-201-3/+3
| | | | | | | | | I accidentally exposed a bug in MCExpr::evaluateAsRelocatableImpl() with the test file added in: http://reviews.llvm.org/rL269977 Differential Revision: http://reviews.llvm.org/D20434 llvm-svn: 270218
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