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* [X86][BMI]: Adding full coverage of MC encoding for the BMI isa set.<NFC>Gadi Haber2017-12-134-0/+1104
| | | | | | | | | | | | | NFC. Adding MC regressions tests to cover the BMI1 and BMI2 ISA sets both 32 and 64 bit. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets. started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, craig.topper, m_zuckerman, RKSimon Differential Revision: https://reviews.llvm.org/D41106 Change-Id: I033ce137b5b82d36e1e601cd5e0534637b43a4a9 llvm-svn: 320557
* [X86][FMA][FMA4]: Adding full coverage of MC encoding for the FMA, FMA4 isa ↵Gadi Haber2017-12-072-0/+8068
| | | | | | | | | | | | | | sets.<NFC> NFC. Adding MC regressions tests to cover the FMA and FMA4 ISA sets. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets starting revision https://reviews.llvm.org/D39952 Reviewers: craig.topper, RKSimon, zvi Differential Revision: https://reviews.llvm.org/D40880 Change-Id: Ie39c0edce69ad647076b3d4e816948b2b6e1a9e4 llvm-svn: 320016
* [X86][X87]: Adding full coverage of MC encoding for all X87 ISA Sets.<NFC>Gadi Haber2017-12-072-0/+3236
| | | | | | | | | | | | | NFC. Currently, not all the X86 ISA Sets are covered by the MC regressions tests for X86. A full coverage needs to be added for each ISA set and for both 32bit and 64bit instructions + registers. This patch includes MC assembly tests for the X87 32bit and 64bit. Reviewers: craigt, RKSimon, zvi Differential Revision: https://reviews.llvm.org/D39952 Change-Id: I55e1719c09a70644a6a4073c720cb5341c80fee9 llvm-svn: 320015
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-2/+2
| | | | | | | | | | | | | | | | As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
* [X86] Fix copy paste mistake in test case for r319612.Craig Topper2017-12-021-1/+1
| | | | llvm-svn: 319613
* [X86] Teach the assembler to support %db8-%db15 as aliases for %dr8-%dr15.Craig Topper2017-12-021-0/+3
| | | | llvm-svn: 319612
* [X86] Support %dr8-%dr15 in the assembler.Craig Topper2017-12-021-0/+3
| | | | | | Apparently I failed to make this work when I fixed it in the disassembler way back in r224862. llvm-svn: 319611
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-3/+3
| | | | | | | | | | | As part of the unification of the debug format and the MIR format, always print registers as lowercase. * Only debug printing is affected. It now follows MIR. Differential Revision: https://reviews.llvm.org/D40417 llvm-svn: 319187
* Control-Flow Enforcement Technology - Shadow Stack support (LLVM side)Oren Ben Simhon2017-11-261-0/+169
| | | | | | | | | | | | | | | | | | Shadow stack solution introduces a new stack for return addresses only. The HW has a Shadow Stack Pointer (SSP) that points to the next return address. If we return to a different address, an exception is triggered. The shadow stack is managed using a series of intrinsics that are introduced in this patch as well as the new register (SSP). The intrinsics are mapped to new instruction set that implements CET mechanism. The patch also includes initial infrastructure support for IBT. For more information, please see the following: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf Differential Revision: https://reviews.llvm.org/D40223 Change-Id: I4daa1f27e88176be79a4ac3b4cd26a459e88fed4 llvm-svn: 318996
* [x86][icelake]GFNICoby Tayree2017-11-263-0/+786
| | | | | | | | | | galois field arithmetic (GF(2^8)) insns: gf2p8affineinvqb gf2p8affineqb gf2p8mulb Differential Revision: https://reviews.llvm.org/D40373 llvm-svn: 318993
* [x86][icelake]BITALGCoby Tayree2017-11-232-0/+168
| | | | | | | | | | 2/3 vpshufbitqmb encoding 3/3 vpshufbitqmb intrinsics Differential Revision: https://reviews.llvm.org/D40222 llvm-svn: 318904
* Avoid unecessary opsize byte in segment move to memoryNirav Dave2017-11-213-14/+14
| | | | | | | | | | | | | | | | | Segment moves to memory are always 16-bit. Remove invalid 32 and 64 bit variants. Recommiting with missing clang inline assembly test change. Fixes PR34478. Reviewers: rnk, craig.topper Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D39847 llvm-svn: 318797
* [x86][icelake]BITALGCoby Tayree2017-11-212-0/+340
| | | | | | | vpopcnt{b,w} Differential Revision: https://reviews.llvm.org/D40213 llvm-svn: 318748
* [x86][icelake]VNNICoby Tayree2017-11-212-0/+1348
| | | | | | | | | Introducing Vector Neural Network Instructions, consisting of: vpdpbusd{s} vpdpwssd{s} Differential Revision: https://reviews.llvm.org/D40208 llvm-svn: 318746
* [x86][icelake]vbmi2Coby Tayree2017-11-212-0/+5378
| | | | | | | | | | | introducing vbmi2, consisting of vpcompress{b,w} vpexpand{b,w} vpsh{l,r}d{w,d,q} vpsh{l,r}dv{w,d,q} Differential Revision: https://reviews.llvm.org/D40206 llvm-svn: 318745
* [x86][icelake]vpclmulqdq introductionCoby Tayree2017-11-213-0/+117
| | | | | | | an icelake promotion of pclmulqdq Differential Revision: https://reviews.llvm.org/D40101 llvm-svn: 318741
* [x86][icelake]VAES introductionCoby Tayree2017-11-213-0/+454
| | | | | | | an icelake promotion of AES Differential Revision: https://reviews.llvm.org/D40078 llvm-svn: 318740
* Revert r318678 to fix Clang testRichard Trieu2017-11-213-14/+14
| | | | | | r318678 caused the Clang test CodeGen/ms-inline-asm.c to start failing. llvm-svn: 318710
* [X86] Avoid unecessary opsize byte in segment move to memoryNirav Dave2017-11-203-14/+14
| | | | | | | | | | | | | | | | | Summary: Segment moves to memory are always 16-bit. Remove invalid 32 and 64 bit variants. Fixes PR34478. Reviewers: rnk, craig.topper Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D39847 llvm-svn: 318678
* [X86] Limit NOPs to 7 bytes when 'slm' is spelled 'silvermont'.Craig Topper2017-11-131-0/+1
| | | | | | We support 2 spelling for silvermont and we should accept both here. llvm-svn: 318023
* [X86][AsmParser] Treat '%' as the modulo operator under Intel syntaxReid Kleckner2017-10-311-1/+6
| | | | | | | | | | It can't be a register prefix, anyway. This is consistent with the masm docs on MSDN: https://msdn.microsoft.com/en-us/library/t4ax90d2.aspx This is a straight-forward extension of our support for "MOD" implemented in https://reviews.llvm.org/D33876 / r306425 llvm-svn: 317011
* [X86] Teach the assembly parser to warn on duplicate registers in gather ↵Craig Topper2017-10-261-0/+19
| | | | | | | | | | instructions. Fixes PR32238. Differential Revision: https://reviews.llvm.org/D39077 llvm-svn: 316700
* [X86] Add PTWRITE instruction for assembler and disassembler.Craig Topper2017-10-232-0/+24
| | | | llvm-svn: 316333
* [X86] Add RDPID instruction for assembler and disassembler.Craig Topper2017-10-232-0/+8
| | | | llvm-svn: 316332
* Try to make crlf portable to other printf implementationsReid Kleckner2017-10-172-1/+3
| | | | llvm-svn: 315961
* [MC] Lex CRLF as one tokenReid Kleckner2017-10-161-0/+5
| | | | | | | | | | This will prevent doubling of line endings when parsing assembly and emitting assembly. Otherwise we'd parse the directive, consume the end of statement, hit the next end of statement, and emit a fresh newline. llvm-svn: 315943
* This patch is a result of D37262: The issues with X86 prefixes. It closes ↵Andrew V. Tischenko2017-10-162-20/+10
| | | | | | PR7709, PR17697, PR19251, PR32809 and PR21640. There could be other bugs closed by this patch. llvm-svn: 315899
* [MC] Properly diagnose badly scoped .cfi_ directivesReid Kleckner2017-10-101-0/+18
| | | | | | | | | | Removes two report_fatal_errors. Implement this by removing EmitCFICommon, and do the checking in getCurrentDwarfFrameInfo. Have the callers check for null before dereferencing it. llvm-svn: 315264
* [X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMemCraig Topper2017-10-013-12/+12
| | | | | | | | | | | | | | | | | | | Summary: Intel documentation shows the memory operand as the first operand. But we currently treat it as the second operand. Conceptually the order doesn't matter since it doesn't write memory. We have aliases to parse with the operands in either order and the isel matching is commutable. For the register&register form order does matter for the assembly parser. PR22995 was previously filed and fixed by changing the register&register form from MRMSrcReg to MRMDestReg to match gas. Ideally the memory form should match by using MRMDestMem. I believe this supercedes D38025 which was trying to switch the register&register form back to pre-PR22995. Reviewers: aymanmus, RKSimon, zvi Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38120 llvm-svn: 314639
* [x86][AsmParser] Allow some more MS size directivesCoby Tayree2017-09-281-0/+7
| | | | | | | MS allows the following size directives: float/double and long as synonymous to dword/qword and dword, respectively. Differential Revision: https://reviews.llvm.org/D37190 llvm-svn: 314410
* [X86][AsmParser] fix PR32035Coby Tayree2017-09-271-0/+5
| | | | | | Differential Revision: https://reviews.llvm.org/D37473 llvm-svn: 314295
* [X86] [ASM INTEL SYNTAX] fix for incorrect assembler code generation when ↵Konstantin Belochapka2017-09-251-0/+49
| | | | | | | | | x86-asm-syntax=intel (PR34617). Fix for incorrect code generation when x86-asm-syntax=intel. Differential Revision: https://reviews.llvm.org/D37945 llvm-svn: 314140
* [X86] [MC] fixed non optimal encoding of instruction memory operand (PR24038).Konstantin Belochapka2017-09-221-0/+12
| | | | | | | Fixed suboptimal encoding of instruction memory operand when assembler is used to select 32 bit fixup rather than 8 bit immediate for encoding memory offset value. Differential Revision: https://reviews.llvm.org/D38117 llvm-svn: 314044
* [dwarfdump] Make .eh_frame an alias for .debug_frameJonas Devlieghere2017-09-181-1/+1
| | | | | | | | | | | | | | | | | | | | This patch makes the `.eh_frame` extension an alias for `.debug_frame`. Up till now it was only possible to dump the section using objdump, but not with dwarfdump. Since the two are essentially interchangeable, we dump whichever of the two is present. As a workaround, this patch also adds parsing for 3 currently unimplemented CFA instructions: `DW_CFA_def_cfa_expression`, `DW_CFA_expression`, and `DW_CFA_val_expression`. Because I lack the required knowledge, I just parse the fields without actually creating the instructions. Finally, this also fixes the typo in the `.debug_frame` section name which incorrectly contained a trailing `s`. Differential revision: https://reviews.llvm.org/D37852 llvm-svn: 313530
* llvm-dwarfdump: Replace -debug-dump=sect option with individual options.Adrian Prantl2017-09-112-3/+3
| | | | | | | | | | | | | | | | | | | | | | As discussed on llvm-dev in http://lists.llvm.org/pipermail/llvm-dev/2017-September/117301.html this changes the command line interface of llvm-dwarfdump to match the one used by the dwarfdump utility shipping on macOS. In addition to being shorter to type this format also has the advantage of allowing more than one section to be specified at the same time. In a nutshell, with this change $ llvm-dwarfdump --debug-dump=info $ llvm-dwarfdump --debug-dump=apple-objc becomes $ dwarfdump --debug-info --apple-objc Differential Revision: https://reviews.llvm.org/D37714 llvm-svn: 312970
* [LLVM][x86][Inline Asm] support for GCC style inline asm - Y<x> constraintsCoby Tayree2017-08-241-0/+83
| | | | | | | | | | This patch is intended to enable the use of basic double letter constraints used in GCC extended inline asm {Yi Y2 Yz Y0 Ym Yt}. Supersedes D35204 Clang counterpart: D36371 Differential Revision: https://reviews.llvm.org/D36369 llvm-svn: 311644
* [X86AsmParser] Refactoring, (almost) NFC.Coby Tayree2017-08-243-59/+28
| | | | | | | | | | Some refactoring to X86AsmParser, mostly regarding the way rewrites are conducted. Mainly, we try to concentrate all the rewrite effort under one hood, so it'll hopefully be less of a mess and easier to maintain and understand. naturally, some frontend tests were affected: D36794 Differential Revision: https://reviews.llvm.org/D36793 llvm-svn: 311639
* [X86] Allow xacquire/xrelease prefixesCoby Tayree2017-08-212-0/+24
| | | | | | | Allow those prefixes on assembly code Differential Revision: https://reviews.llvm.org/D36845 llvm-svn: 311309
* [X86][AsmParser][AVX512] Error appropriately when K0 is tried as a write-maskCoby Tayree2017-08-132-3/+5
| | | | | | | | | K0 isn't expected as a write-mask, so provide a detailed error here, instead of the more generic one (invalid op for insn) Conforms with gas Differential Revision: https://reviews.llvm.org/D36570 llvm-svn: 310789
* [X86][Asm]Allow far jmp/call to be picked when using explicit FWORD size ↵Coby Tayree2017-08-092-5/+17
| | | | | | | | | | | specifier Currently, far jmp/call which utilizes a 48bit memory operand would have been invoked via the 'lcall/ljmp' mnemonic (intel style). This patch align those variants to formal intel spec Differential Revision: https://reviews.llvm.org/D35846 llvm-svn: 310485
* [AsmParser][AVX512]Enhance OpMask/Zero/Merge syntax check rubostnessCoby Tayree2017-08-092-1/+15
| | | | | | | | Adopt a more strict approach regarding what marks should/can appear after a destination register, when operating upon an AVX512 platform. Differential Revision: https://reviews.llvm.org/D35785 llvm-svn: 310467
* X86 Asm uses assertions instead of proper diagnostic. This patch fixes that.Andrew V. Tischenko2017-07-253-1/+94
| | | | | | Differential Revision: https://reviews.llvm.org/D35115 llvm-svn: 308972
* [X86] Add nopq instruction which is a rex encoded version of nopl for gas ↵Craig Topper2017-07-222-0/+9
| | | | | | compatibility. llvm-svn: 308818
* [X86] Add register form of NOPL and NOPW for assembler/disassembler.Craig Topper2017-07-221-0/+8
| | | | | | Fixes PR32805. llvm-svn: 308817
* revert: [llvm] r308609 - This patch added some test cases to demonsrate the ↵Simon Pilgrim2017-07-202-82/+1
| | | | | | issues described in Bug 33848 - X86 Asm does not support symbolic names inside address calculation. llvm-svn: 308622
* This patch added some test cases to demonsrate the issues described in Bug ↵Andrew V. Tischenko2017-07-202-1/+82
| | | | | | 33848 - X86 Asm does not support symbolic names inside address calculation. llvm-svn: 308609
* [llvm] Remove redundant check-prefix=CHECK from tests. NFC.Mandeep Singh Grang2017-07-171-2/+2
| | | | | | | | | | | | Reviewers: t.p.northover, oren_ben_simhon, niravd, mcrosier Reviewed By: oren_ben_simhon, mcrosier Subscribers: nhaehnle, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D35466 llvm-svn: 308193
* Fix PR33625.Rafael Espindola2017-06-281-0/+12
| | | | | | We were failing to convert this expression to pcrel. llvm-svn: 306573
* [X86][AsmParser][MS-compatability] Binary/Unary operators enhancementsCoby Tayree2017-06-271-0/+17
| | | | | | | | | | | Introducing MOD binary operator https://msdn.microsoft.com/en-us/library/hha180wt.aspx Enhancing unary operators NEG and NOT, to support more complex patterns Differential Revision: https://reviews.llvm.org/D33876 llvm-svn: 306425
* Add a common error checking for some invalid expressions.Rafael Espindola2017-06-221-1/+1
| | | | | | | This refactors a bit of duplicated code and fixes an assertion failure on ELF. llvm-svn: 306035
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