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* [X86] movdiri and movdir64b instructionsGabor Buella2018-04-233-0/+56
| | | | | Reviewers: craig.topper llvm-svn: 330638
* [X86] Remove DATA32_PREFIX. Hack the printing for DATA16_PREFIX to print ↵Craig Topper2018-04-221-3/+3
| | | | | | | | | | 'data32' in 16-bit mode. Hack the asm parser to convert 'data32' to 'data16' in 16-bit mode. Improve the error messages to match GNU assembler. This also allows us to remove the hack from the disassembler table building. llvm-svn: 330531
* [X86] WaitPKG instructionsGabor Buella2018-04-203-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Three new instructions: umonitor - Sets up a linear address range to be monitored by hardware and activates the monitor. The address range should be a writeback memory caching type. umwait - A hint that allows the processor to stop instruction execution and enter an implementation-dependent optimized state until occurrence of a class of events. tpause - Directs the processor to enter an implementation-dependent optimized state until the TSC reaches the value in EDX:EAX. Also modifying the description of the mfence instruction, as the rep prefix (0xF3) was allowed before, which would conflict with umonitor during disassembly. Before: $ echo 0xf3,0x0f,0xae,0xf0 | llvm-mc -disassemble .text mfence After: $ echo 0xf3,0x0f,0xae,0xf0 | llvm-mc -disassemble .text umonitor %rax Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45253 llvm-svn: 330462
* [X86] Introduce cldemote instructionGabor Buella2018-04-132-0/+15
| | | | | | | | | | | | | | Hint to hardware to move the cache line containing the address to a more distant level of the cache without writing back to memory. Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45256 llvm-svn: 329992
* [X86] Describe wbnoinvd instructionGabor Buella2018-04-113-0/+12
| | | | | | | | | | | | | | | Similar to the wbinvd instruction, except this one does not invalidate caches. Ring 0 only. The encoding matches a wbinvd instruction with an F3 prefix. Reviewers: craig.topper, zvi, ashlykov Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D43816 llvm-svn: 329847
* [X86] Added support for nocf_check attribute for indirect Branch TrackingOren Ben Simhon2018-03-171-0/+12
| | | | | | | | | | | | | | | X86 Supports Indirect Branch Tracking (IBT) as part of Control-Flow Enforcement Technology (CET). IBT instruments ENDBR instructions used to specify valid targets of indirect call / jmp. The `nocf_check` attribute has two roles in the context of X86 IBT technology: 1. Appertains to a function - do not add ENDBR instruction at the beginning of the function. 2. Appertains to a function pointer - do not track the target function of this pointer by adding nocf_check prefix to the indirect-call instruction. This patch implements `nocf_check` context for Indirect Branch Tracking. It also auto generates `nocf_check` prefixes before indirect branchs to jump tables that are guarded by range checks. Differential Revision: https://reviews.llvm.org/D41879 llvm-svn: 327767
* [X86] Add assembler/disassembler support for blendm with zero masking and ↵Craig Topper2018-02-232-0/+184
| | | | | | | | broacast. Fixes PR31617 llvm-svn: 325957
* [MC] - Don't crash on unclosed frame.George Rimar2018-02-201-0/+10
| | | | | | | | | | | | | | | | llvm-mc can crash when there is cfi_startproc without cfi_end_proc: .text .globl foo foo: .cfi_startproc Testcase shows the issue, patch fixes it. Differential revision: https://reviews.llvm.org/D43456 llvm-svn: 325564
* [X86][CET]: Adding full coverage of MC encoding for the CET instructions.<NFC>Gadi Haber2018-02-202-0/+300
| | | | | | | | | | | | NFC. Adding MC regressions tests to cover the CET instructions. This patch is part of a larger task to cover MC encoding of all X86 isa sets started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, craig.topper, RKSimon, AndreiGrischenko, oren_ben_simhon Differential Revision: https://reviews.llvm.org/D41329 Change-Id: I9c133d4ba07508ce8fd738a1230edd586e2c2f1b llvm-svn: 325561
* [X86] Change 32 and 64 bit versions of LSL instruction have a 16-bit memory ↵Craig Topper2018-02-151-0/+8
| | | | | | | | operand. This matches the Intel and AMD documentation and is consistent with the LAR instruction. llvm-svn: 325197
* [X86] Dont' allow 'outs' and 'ins' in at&t syntax without suffixes.Craig Topper2018-02-142-9/+0
| | | | | | The match would be ambiguous, but at&t asm parsing doesn't support ambiguous matches and will just return the first. llvm-svn: 325192
* [X86] Don't use 64 bit hex constants in a 32 bit assembler test.Craig Topper2018-02-141-51/+0
| | | | llvm-svn: 325191
* [X86] Reverse the operand order of invlpga in at&t syntax to match gas.Craig Topper2018-02-144-8/+8
| | | | llvm-svn: 325190
* [X86] Don't swap argument on BOUND instruction in at&t syntax.Craig Topper2018-02-143-20/+20
| | | | | | | | | | | | The bound instruction does not have reversed operands in gas. Fixes PR27653. Patch by Maya Madhavan. Differential Revision: https://reviews.llvm.org/D43243 llvm-svn: 325178
* [MC] Issue error message when data region is not terminatedGerolf Hoflehner2018-02-121-0/+8
| | | | llvm-svn: 324868
* [X86][MC] Fix assembling rip-relative addressing + immediate displacementsFrancis Visoiu Mistrih2018-02-091-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In the rare case where the input contains rip-relative addressing with immediate displacements, *and* the instruction ends with an immediate, we encode the instruction in the wrong way: movl $12345678, 0x400(%rdi) // all good, no rip-relative addr movl %eax, 0x400(%rip) // all good, no immediate at the end of the instruction movl $12345678, 0x400(%rip) // fails, encodes address as 0x3fc(%rip) Offset is a label: movl $12345678, foo(%rip) we want to account for the size of the immediate (in this case, $12345678, 4 bytes). Offset is an immediate: movl $12345678, 0x400(%rip) we should not account for the size of the immediate, assuming the immediate offset is what the user wanted. Differential Revision: https://reviews.llvm.org/D43050 llvm-svn: 324772
* [X86][MC]: Adding test coverage of MC encoding for several small ↵Gadi Haber2018-02-0823-0/+1602
| | | | | | | | | | | | | | | | extensions.<NFC> NFC. Adding MC regressions tests to cover several small x86 extensions as follows: CLWB, CLZERO, F16C, INVPCID, PKU, POPCNT, RTM, SGX, SHA, SVM, VMFUNC, VTX This patch is part of a larger task to cover MC encoding of all X86 isa sets started in revision: https://reviews.llvm.org/D39952 Reviewers: RKSimon, craig.topper, zvi, AndreiGrischenko Differential Revision: https://reviews.llvm.org/D41388 Change-Id: I254508cd17faca00b780be0fc2abf6c71b61faab llvm-svn: 324595
* [X86] Remove checks for FeatureAVX512 from the X86 assembly parser. Remove ↵Craig Topper2018-02-0243-51/+45
| | | | | | | | | | | | | | | | | | | | | mcpu/mattr from assembly test command lines. Summary: We should always be able to accept AVX512 registers and instructions in llvm-mc. The only subtarget mode that should be checked is 16-bit vs 32-bit vs 64-bit mode. I've also removed all the mattr/mcpu lines from test RUN lines to be consistent with this. Most were due to AVX512, but a few were for other features. Fixes PR36202 Reviewers: RKSimon, echristo, bkramer Reviewed By: echristo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42824 llvm-svn: 324106
* [X86] Emit 11-byte or 15-byte NOPs on recent AMD targets, else default to ↵Simon Pilgrim2018-01-295-21/+45
| | | | | | | | | | | | 10-byte NOPs (PR22965) We currently emit up to 15-byte NOPs on all targets (apart from Silvermont), which stalls performance on some targets with decoders that struggle with 2 or 3 more '66' prefixes. This patch flags recent AMD targets (btver1/znver1) to still emit 15-byte NOPs and bdver* targets to emit 11-byte NOPs. All other targets now emit 10-byte NOPs apart from SilverMont CPUs which still emit 7-byte NOPS. Differential Revision: https://reviews.llvm.org/D42616 llvm-svn: 323693
* Add triples or specify REQUIRES: default_triple to some testsJustin Bogner2018-01-271-1/+1
| | | | | | | These were all failing when building the X86 backend but specifying LLVM_DEFAULT_TARGET_TRIPLE=''. llvm-svn: 323608
* [X86] Teach Intel syntax InstPrinter to print lock prefixes that have been ↵Craig Topper2018-01-251-0/+6
| | | | | | | | parsed from the asm parser. The asm parser puts the lock prefix in the MCInst flags so we need to check that in addition to TSFlags. This matches what the ATT printer does. llvm-svn: 323469
* [X86] Remove 64/128/256 from MMX/SSE/AVX instruction names for overall ↵Craig Topper2018-01-251-1/+1
| | | | | | | | | | consistency. NFC MMX instrutions all start with MMX_ so the 64 isn't needed for disambigutation. SSE/AVX1 instructions are assumed 128-bit so we don't need to say 128. AVX2 instructions should use a Y to indicate 256-bits. llvm-svn: 323402
* [X86] Adjust names of PINSRW/PEXTRW intructions between MMX/SSE/AVX/AVX512 ↵Craig Topper2018-01-241-2/+2
| | | | | | for consistency and to maybe enable more regular expression compaction in the scheduler models. NFCI llvm-svn: 323352
* Allow usage of X86-prefixes as separate instrs.Andrew V. Tischenko2018-01-171-1/+37
| | | | | | Differential Revision: https://reviews.llvm.org/D42102 llvm-svn: 322623
* [X86][I86,I186,I286,I386,I486,PPRO, MMX]: Adding full coverage of MC ↵Gadi Haber2018-01-1614-0/+16124
| | | | | | | | | | | | | | | encoding for the I86, I186, I286, I386, I486, PPRO and MMX isa sets.<NFC> NFC. Adding MC regressions tests to cover the I86, I186, I286, I386, I486, PPRO and MMX isa sets. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets. Started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, RKSimon, AndreiGrischenko, craig.topper Differential Revision: https://reviews.llvm.org/D40879 Change-Id: I231a35861611bfd3d23c74cc59507373f021a629 llvm-svn: 322544
* [X86][XSAVE]: Adding full coverage of MC encoding for the XSAVE isa sets.<NFC>Gadi Haber2018-01-1611-0/+614
| | | | | | | | | | | | NFC. Adding MC regressions tests to cover the XSAVE ISA sets. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, RKSimon, AndreiGrischenko, craig.topper Differential Revision: https://reviews.llvm.org/D41282 Change-Id: I325bf8f421f78c80179a04fc39033366759cbe45 llvm-svn: 322537
* [X86] Make 'xchgq %rax, %rax' an alias for the 0x90 nop encoding to match gas.Craig Topper2018-01-161-2/+2
| | | | | | Previously we encoded it as 0x48 0x90. llvm-svn: 322531
* [X86][AVX512F_512]: Adding full coverage of MC encoding for the AVX512F 512 ↵Gadi Haber2018-01-152-0/+70464
| | | | | | | | | | | | | | | bits isa sets.<NFC> NFC. Adding MC regressions tests to cover the AVX512F_512 isa sets both 32 and 64 bit. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets. started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, craig.topper, RKSimon, AndreiGrischenko Differential Revision: https://reviews.llvm.org/D41172 Change-Id: I46aa33dd967d63d33f67d1988ad42d8df2081e39 llvm-svn: 322471
* [X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics.Craig Topper2018-01-121-39/+39
| | | | | | While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
* Implementation of X86Operand::print.Andrew V. Tischenko2018-01-111-40/+39
| | | | | | Differential Revision: https://reviews.llvm.org/D41610 llvm-svn: 322267
* Use a MCExpr for the size of MCFillFragment.Rafael Espindola2018-01-091-0/+17
| | | | | | | This allows the size to be found during ralaxation. This fixes pr35858. llvm-svn: 322131
* Add a test.Rafael Espindola2018-01-091-0/+4
| | | | | | Currently we don't have any tests for this error case. llvm-svn: 322129
* Instrument Control Flow For Indirect Branch TrackingOren Ben Simhon2018-01-091-1/+9
| | | | | | | | | | | | | CET (Control-Flow Enforcement Technology) introduces a new mechanism called IBT (Indirect Branch Tracking). According to IBT, each Indirect branch should land on dedicated ENDBR instruction (End Branch). The new pass adds ENDBR instructions for every indirect jmp/call (including jumps using jump tables / switches). For more information, please see the following: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf Differential Revision: https://reviews.llvm.org/D40482 Change-Id: Icb754489faf483a95248f96982a4e8b1009eb709 llvm-svn: 322062
* [X86] Remove memory forms of EVEX encoded vcvttss2si/vcvttsd2si from asm ↵Craig Topper2018-01-061-8/+8
| | | | | | | | matcher table. This is also needed to fix PR35837. llvm-svn: 321946
* [X86] Remove memory forms of EVEX encoded vcvtsd2si/vcvtss2si from the ↵Craig Topper2018-01-061-4/+4
| | | | | | | | | | assembler matcher table We should always prefer the VEX encoded version of these instructions. There is no advantage to the EVEX version. Fixes PR35837. llvm-svn: 321939
* [X86] When parsing rounding mode operands, provide a proper end location so ↵Craig Topper2018-01-061-0/+3
| | | | | | we don't crash when trying to print an error message using it. llvm-svn: 321930
* [X86] Add vcvtsd2sil/vcvtsd2siq etc. InstAliases to the EVEX-encoded ↵Craig Topper2018-01-051-0/+64
| | | | | | | | instructions. This matches their VEX equivalents. llvm-svn: 321912
* [X86] Add InstAliases for 'vmovd' with GR64 registers to select EVEX encoded ↵Craig Topper2018-01-051-0/+8
| | | | | | | | | | instructions as well. Without this we allow "vmovd %rax, %xmm0", but not "vmovd %rax, %xmm16" This exists due to continue a silly bug where really old versions of the GNU assembler required movd instead of movq on these instructions. This compatibility hack then crept forward to avx version too, but we didn't propagate it to avx512. llvm-svn: 321903
* [X86] Stop printing moves between VR64 and GR64 with 'movd' mnemonic. Use ↵Craig Topper2018-01-052-8/+32
| | | | | | | | 'movq' instead. This behavior existed to work with an old version of the gnu assembler on MacOS that only accepted this form. Newer versions of GNU assembler and the current LLVM derived version of the assembler on MacOS support movq as well. llvm-svn: 321898
* Fix incorrect operand sizes for some MMX instructions: punpcklwd, punpcklbw ↵Andrew V. Tischenko2017-12-293-2/+20
| | | | | | | | and punpckldq. Differential Revision: https://reviews.llvm.org/D41595 llvm-svn: 321549
* [X86][PREFETCH]: Adding full coverage of MC encoding for the PREFETCH isa ↵Gadi Haber2017-12-282-0/+339
| | | | | | | | | | | | | | sets.<NFC> NFC. Adding MC regressions tests to cover the PREFETCH isa sets for both 32 and 64 bit. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, craig.topper, RKSimon, AndreiGrischenko Differential Revision: https://reviews.llvm.org/D41161 Change-Id: Icdc8c5fb68c414de7d2cfdb50da1cc6763d9932a llvm-svn: 321524
* A special test to demonstrate debug logging for asm matcher.Andrew V. Tischenko2017-12-271-0/+52
| | | | llvm-svn: 321497
* [X86][RD]: Adding full coverage of MC encoding for RD isa sets.<NFC>Gadi Haber2017-12-279-0/+98
| | | | | | | | | | | | NFC. Adding MC regressions tests to cover RDPMC, RDRAND, RDRAND, RDSEED, RDTSCP, DWRFSGS isa sets. This patch is part of a larger task to cover MC encoding of all X86 isa sets started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, craig.topper, RKSimon, AndreiGrischenk Differential Revision: https://reviews.llvm.org/D41328 Change-Id: Ie97b397546e6b1ed180c6abd7b41fccb136d2b82 llvm-svn: 321476
* It's a fix for Bug 35741 - can't use comments after x86 prefixes.Andrew V. Tischenko2017-12-261-0/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D41579 llvm-svn: 321459
* [X86] Add prefetchwt1 instruction and overhaul priorities and isel enabling ↵Craig Topper2017-12-221-0/+2
| | | | | | | | | | | | | | for prefetch instructions. Previously prefetch was only considered legal if sse was enabled, but it should be supported with 3dnow as well. The prfchw flag now imply at least some form of prefetch without the write hint is available, either the sse or 3dnow version. This is true even if 3dnow and sse are explicitly disabled. Similarly prefetchwt1 feature implies availability of prefetchw and the the prefetcht0/1/2/nta instructions. This way we can support _MM_HINT_ET0 using prefetchw and _MM_HINT_ET1 with prefetchwt1. And its assumed that if we have levels for the write hint we would have levels for the non-write hint, thus why we enable the sse prefetch instructions. I believe this behavior is consistent with gcc. I've updated the prefetch.ll to test all of these combinations. llvm-svn: 321335
* [X86][CLFLUSH]: Adding full coverage of MC encoding for the CLFLUSH isa ↵Gadi Haber2017-12-204-0/+104
| | | | | | | | | | | | | | sets.<NFC> NFC. Adding MC regressions tests to cover the CLFLSH and CLFLUSHOPT isa sets. This patch is part of a larger task to cover MC encoding of all X86 isa sets started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, RKSimon, craig.topper, m_zuckerman Differential Revision: https://reviews.llvm.org/D41331 Change-Id: Ifa643dd52f1b7184c52bc1806038dc74b234fc65 llvm-svn: 321153
* [X86] Don't use NOPL when the assembler is passed an empty CPU string. ↵Craig Topper2017-12-189-20/+20
| | | | | | | | | | Update tests to force a CPU with NOPL Empty string should be equivalent to "generic" which doesn't allow NOPL. Force tests to use specificy 'pentiumpro' to guarantee NOPL. Fixes PR35686 llvm-svn: 321026
* [X86] Fix XSAVE64 and similar instructions to not be allowed by the ↵Craig Topper2017-12-151-8/+0
| | | | | | | | | | assembler in 32-bit mode. There was a top level "let Predicates =" in the .td file that was overriding the Requires on each instruction. I've added an assert to the code emitter to catch more cases like this. I'm sure this isn't the only place where the right predicates aren't being applied. This assert already found that we don't block btq/btsq/btrq in 32-bit mode. llvm-svn: 320830
* [X86][AVX][AVX2]: Adding full coverage of MC encoding for the AVX, AVX2 isa ↵Gadi Haber2017-12-144-0/+40436
| | | | | | | | | | | | | | | set.<NFC> NFC. Adding MC regressions tests to cover the AVX and AVX2 ISA sets. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets. See revision: https://reviews.llvm.org/D39952 Reviewers: zvi, RKSimon, aymanmus, m_zuckerman Differential Revison: https://reviews.llvm.org/D40287 Change-Id: I304687a2b7abb473f79de99c31fc55c97b2662da llvm-svn: 320716
* [X86][AES]: Adding full coverage of MC encoding for the AES and AVXAES isa ↵Gadi Haber2017-12-144-0/+1016
| | | | | | | | | | | | | | | sets.<NFC> NFC. Adding MC regressions tests to cover the AES and AVXAES ISA sets both 32 and 64 bit. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets. started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, craig.topper, m_zuckerman, RKSimon Differential Revision: https://reviews.llvm.org/D41154 Change-Id: I2564f9797628d0c070c4766f837f399337fb87d2 llvm-svn: 320670
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