| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | [ms-inline asm] Support offsets after segment registers | David Majnemer | 2013-08-27 | 1 | -0/+6 | |
| | | | | | | | | | | | | | | | Summary: MASM let's you do stuff like 'MOV FS:20, EAX' and 'MOV EAX, FS:20' Reviewers: craig.topper, rnk Reviewed By: rnk CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1470 llvm-svn: 189407 | |||||
| * | Add test cases for the various instruction alias and Intel syntax fixes that ↵ | Craig Topper | 2013-07-26 | 1 | -0/+222 | |
| | | | | | | | have gone in lately. llvm-svn: 187188 | |||||
| * | X86: Make the cmov aliases work with intel syntax too. | Benjamin Kramer | 2013-06-13 | 1 | -0/+29 | |
| | | | | | llvm-svn: 183907 | |||||
| * | [x86AsmParser] It's valid to stop parsing an operand at an immediate. | Chad Rosier | 2013-05-09 | 1 | -0/+2 | |
| | | | | | | | rdar://13854369 and PR15944 llvm-svn: 181564 | |||||
| * | Add test case for PR15779, which has previously been fixed. | Chad Rosier | 2013-04-22 | 1 | -1/+2 | |
| | | | | | llvm-svn: 180058 | |||||
| * | [ms-inline asm] Apply the condition code mnemonic aliases to both the Intel and | Chad Rosier | 2013-04-18 | 1 | -0/+30 | |
| | | | | | | | | AT&T dialect. Test case for r179804 as well. rdar://13674398 and PR13340. llvm-svn: 179813 | |||||
| * | [ms-inline asm] Add support for the minus unary operator. Previously, we were | Chad Rosier | 2013-04-17 | 1 | -1/+8 | |
| | | | | | | | | | | | | unable to handle cases such as __asm mov eax, 8*-8. This patch also attempts to simplify the state machine. Further, the error reporting has been improved. Test cases included, but more will be added to the clang side shortly. rdar://13668445 llvm-svn: 179719 | |||||
| * | [ms-inline asm] Add support for numeric displacement expressions in bracketed | Chad Rosier | 2013-04-05 | 1 | -1/+38 | |
| | | | | | | | | | | | | | | | | | | | | | | | memory operands. Essentially, this layers an infix calculator on top of the parsing state machine. The scale on the index register is still expected to be an immediate __asm mov eax, [eax + ebx*4] and will not work with more complex expressions. For example, __asm mov eax, [eax + ebx*(2*2)] The plus and minus binary operators assume the numeric value of a register is zero so as to not change the displacement. Register operands should never be an operand for a multiply or divide operation; the scale*indexreg expression is always replaced with a zero on the operand stack to prevent such a case. rdar://13521380 llvm-svn: 178881 | |||||
| * | [ms-inline asm] Extend support for parsing Intel bracketed memory operands that | Chad Rosier | 2013-01-14 | 1 | -9/+191 | |
| | | | | | | | | have an arbitrary ordering of the base register, index register and displacement. rdar://12527141 llvm-svn: 172484 | |||||
| * | Make x86 asm parser to check for xmm vs ymm for index register in gather ↵ | Craig Topper | 2012-07-18 | 1 | -0/+2 | |
| | | | | | | | instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. llvm-svn: 160420 | |||||
| * | Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320] | Devang Patel | 2012-01-27 | 1 | -0/+2 | |
| | | | | | llvm-svn: 149142 | |||||
| * | Intel syntax: Robustify parsing of memory operand's displacement experssion. | Devang Patel | 2012-01-23 | 1 | -2/+4 | |
| | | | | | llvm-svn: 148737 | |||||
| * | Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI] | Devang Patel | 2012-01-23 | 1 | -1/+3 | |
| | | | | | llvm-svn: 148721 | |||||
| * | Intel syntax: Parse segment registers. | Devang Patel | 2012-01-23 | 1 | -0/+2 | |
| | | | | | llvm-svn: 148712 | |||||
| * | Intel syntax: Robustify register parsing. | Devang Patel | 2012-01-20 | 1 | -0/+2 | |
| | | | | | llvm-svn: 148591 | |||||
| * | Process instructions after match to select alternative encoding which may be ↵ | Devang Patel | 2012-01-18 | 1 | -0/+24 | |
| | | | | | | | more desirable. llvm-svn: 148431 | |||||
| * | Intel syntax: Fix parser match class to check memory operand size. | Devang Patel | 2012-01-17 | 1 | -0/+2 | |
| | | | | | llvm-svn: 148338 | |||||
| * | Intel syntax: Parse "BYTE PTR [RDX + RCX]" | Devang Patel | 2012-01-17 | 1 | -0/+2 | |
| | | | | | llvm-svn: 148334 | |||||
| * | Intel syntax: Do not unncessarily create plus expression for memory operand ↵ | Devang Patel | 2012-01-17 | 1 | -0/+2 | |
| | | | | | | | displacement. llvm-svn: 148321 | |||||
| * | Intel syntax: Ignore mnemonic aliases. | Devang Patel | 2012-01-17 | 1 | -0/+8 | |
| | | | | | llvm-svn: 148316 | |||||
| * | Intel syntax: Robustify memory operand parsing. | Devang Patel | 2012-01-17 | 1 | -0/+8 | |
| | | | | | llvm-svn: 148312 | |||||
| * | Add new test. | Devang Patel | 2012-01-13 | 1 | -0/+10 | |
| llvm-svn: 148128 | ||||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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