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* Sparc: support the "set" synthetic instruction.James Y Knight2015-05-181-0/+17
| | | | | | | | | This pseudo-instruction expands into 'sethi' and 'or' instructions, or, just one of them, if the other isn't necessary for a given value. Differential Revision: http://reviews.llvm.org/D9089 llvm-svn: 237585
* Sparc: Support PSR, TBR, WIM read/write instructions.James Y Knight2015-05-181-0/+18
| | | | | | Differential Revision: http://reviews.llvm.org/D8971 llvm-svn: 237582
* Sparc: Add the "alternate address space" load/store instructions.James Y Knight2015-05-183-8/+29
| | | | | | | | | | | | | | | | | | - Adds support for the asm syntax, which has an immediate integer "ASI" (address space identifier) appearing after an address, before a comma. - Adds the various-width load, store, and swap in alternate address space instructions. (ldsba, ldsha, lduba, lduha, lda, stba, stha, sta, swapa) This does not attempt to hook these instructions up to pointer address spaces in LLVM, although that would probably be a reasonable thing to do in the future. Differential Revision: http://reviews.llvm.org/D8904 llvm-svn: 237581
* Add support for the Sparc implementation-defined "ASR" registers.James Y Knight2015-05-181-0/+17
| | | | | | | | | | (Note that register "Y" is essentially just ASR0). Also added some test cases for divide and multiply, which had none before. Differential Revision: http://reviews.llvm.org/D8670 llvm-svn: 237580
* [Sparc] Repair fixups in little endian mode.James Y Knight2015-05-011-0/+18
| | | | | | Differential Revision: http://reviews.llvm.org/D9434 llvm-svn: 236324
* Make Sparc assembler accept parenthesized constant expressions.Douglas Katzman2015-04-291-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D9087 llvm-svn: 236137
* Sparc: Prefer reg+reg address encoding when only one register used.James Y Knight2015-04-292-11/+11
| | | | | | | | | | | Reg+%g0 is preferred to Reg+imm0 by the manual, and is what GCC produces. Futhermore, reg+imm is invalid for the (not yet supported) "alternate address space" instructions. Differential Revision: http://reviews.llvm.org/D8753 llvm-svn: 236107
* Sparc: Add alternate aliases for conditional branch instructions.James Y Knight2015-04-281-0/+24
| | | | llvm-svn: 236042
* Reduce verbiage of lit.local.cfg filesAlp Toker2014-06-091-2/+1
| | | | | | We can just split targets_to_build in one place and make it immutable. llvm-svn: 210496
* TableGen: fix operand counting for aliasesTim Northover2014-05-162-8/+8
| | | | | | | | | | | | | | | | | | | | | TableGen has a fairly dubious heuristic to decide whether an alias should be printed: does the alias have lest operands than the real instruction. This is bad enough (particularly with no way to override it), but it should at least be calculated consistently for both strings. This patch implements that logic: first get the *correct* string for the variant, in the same way as the Matcher, without guessing; then count the number of whitespace chars. There are basically 4 changes this brings about after the previous commits; all of these appear to be good, so I have changed the tests: + ARM64: we print "neg X, Y" instead of "sub X, xzr, Y". + ARM64: we skip implicit "uxtx" and "uxtw" modifiers. + Sparc: we print "mov A, B" instead of "or %g0, A, B". + Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B" llvm-svn: 208969
* [Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc ↵Venkatraman Govindaraju2014-03-021-0/+7
| | | | | | backend. llvm-svn: 202670
* [Sparc] Add return/rett instruction to Sparc backend.Venkatraman Govindaraju2014-03-022-0/+5
| | | | llvm-svn: 202666
* [Sparc] Add fcmpe* instructions to Sparc backend.Venkatraman Govindaraju2014-03-022-0/+21
| | | | llvm-svn: 202661
* [Sparc] Add VIS instructions to sparc backend.Venkatraman Govindaraju2014-03-021-0/+4
| | | | llvm-svn: 202660
* [SparcV9] Adds support for branch on integer register instructions (BPr) and ↵Venkatraman Govindaraju2014-03-021-0/+78
| | | | | | conditional moves on integer register (MOVr/FMOVr). llvm-svn: 202628
* [Sparc] Add support for parsing branches and conditional move instructions ↵Venkatraman Govindaraju2014-03-021-42/+67
| | | | | | with %fcc1-%fcc3 conditional registers. llvm-svn: 202616
* [Sparc] Add support for parsing fcmp with %fcc registers.Venkatraman Govindaraju2014-03-022-3/+18
| | | | llvm-svn: 202610
* [SparcV9] Add support for parsing branch instructions with prediction.Venkatraman Govindaraju2014-03-011-0/+878
| | | | llvm-svn: 202602
* [Sparc] Add support for parsing annulled branch instructions.Venkatraman Govindaraju2014-03-011-0/+116
| | | | llvm-svn: 202599
* [Sparc] Add support for parsing sparcv9 instructions addc/subc/addccc/subccc.Venkatraman Govindaraju2014-03-011-0/+23
| | | | llvm-svn: 202598
* [Sparc] Add missing ALU instruction patterns.Venkatraman Govindaraju2014-03-011-0/+48
| | | | llvm-svn: 202597
* Add support for parsing sun-style section flags in ELFAsmParser.Venkatraman Govindaraju2014-03-011-1/+1
| | | | llvm-svn: 202573
* [Sparc] Implement writeNopData. Emit actual NOP instruction instead of just ↵Venkatraman Govindaraju2014-03-011-0/+11
| | | | | | filling with zeroes. llvm-svn: 202572
* [Sparc] Teach SparcAsmParser to emit correct relocations for PIC code.Venkatraman Govindaraju2014-03-011-0/+49
| | | | llvm-svn: 202571
* [Sparc] Add support for parsing directives in SparcAsmParser.Venkatraman Govindaraju2014-03-012-0/+29
| | | | llvm-svn: 202564
* [Sparc] Emit 'restore' instead of 'restore %g0, %g0, %g0'. This improves the ↵Venkatraman Govindaraju2014-03-011-0/+3
| | | | | | readability of the generated code. llvm-svn: 202563
* [Sparc] Add support for parsing synthetic instruction 'mov'. Venkatraman Govindaraju2014-02-071-0/+5
| | | | llvm-svn: 200965
* [Sparc] Emit correct encoding for atomic instructions. Also, add support for ↵Venkatraman Govindaraju2014-02-071-0/+19
| | | | | | parsing CAS instructions to test the CAS encoding. llvm-svn: 200963
* [Sparc] Add support for sparc relocation types in ELF object file.Venkatraman Govindaraju2014-01-261-0/+13
| | | | llvm-svn: 200112
* [Sparc] Correct quad register list in the asm parser.Venkatraman Govindaraju2014-01-241-0/+6
| | | | | | Add test cases to check parsing of v9 double registers and their aliased quad registers. llvm-svn: 199974
* [Sparc] Add support for parsing floating point instructions.Venkatraman Govindaraju2014-01-121-0/+113
| | | | llvm-svn: 199033
* [Sparc] Add support for parsing jmpl instruction and make indirect call and ↵Venkatraman Govindaraju2014-01-101-0/+13
| | | | | | jmp instructions as aliases to jmpl. llvm-svn: 198909
* [SparcV9] Rename operands in some sparc64 instructions so that TableGen can ↵Venkatraman Govindaraju2014-01-081-0/+38
| | | | | | encode them correctly. llvm-svn: 198740
* [Sparc] Add support for parsing branch instructions and conditional moves.Venkatraman Govindaraju2014-01-082-0/+349
| | | | llvm-svn: 198738
* [Sparc] Add support for parsing sparc asm modifiers such as %hi, %lo etc., Venkatraman Govindaraju2014-01-072-7/+50
| | | | | | Also, correct the offsets for FixupsKindInfo. llvm-svn: 198681
* [Sparc] Add support for parsing memory operands in sparc AsmParser.Venkatraman Govindaraju2014-01-072-0/+81
| | | | llvm-svn: 198658
* Add lit.local.cfg for MC/SparcVenkatraman Govindaraju2014-01-051-0/+4
| | | | llvm-svn: 198536
* [Sparc] Add initial implementation of MC Code emitter for sparc.Venkatraman Govindaraju2014-01-051-0/+72
llvm-svn: 198533
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