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path: root/llvm/test/MC/RISCV/rvi-aliases-valid.s
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* [RISCV] Add additional CSR instruction aliases (imm. operands)Alex Bradbury2018-11-301-0/+20
* [RISCV] Support named operands for CSR instructions.Ana Pazos2018-10-041-7/+7
* [RISCV][MC] Improve parsing of jal/j operandsAlex Bradbury2018-09-201-4/+28
* [RISCV] Fix r341050Alex Bradbury2018-08-301-3/+0
* [RISCV][NFC] Rework CHECK lines in rvi-aliases-valid.sAlex Bradbury2018-08-301-129/+129
* [RISCV] Add mnemonic alias: move, sbreak and scall.Alex Bradbury2018-08-081-0/+11
* [RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], s...Alex Bradbury2018-08-081-0/+38
* [RISCV] Add InstAlias definitions for sgt and sgtuAlex Bradbury2018-06-201-0/+7
* [RISCV] AsmParser support for the li pseudo instructionAlex Bradbury2018-06-071-9/+14
* Revert "[RISCV] implement li pseudo instruction"Alex Bradbury2018-04-181-4/+1
* [RISCV] implement li pseudo instructionAlex Bradbury2018-04-171-1/+4
* [RISCV] Enable emission of alias instructions by defaultAlex Bradbury2017-12-151-4/+4
* [RISCV] Define sfence.vma InstAliases to match the GNU RISC-V toolsAlex Bradbury2017-12-131-0/+7
* [RISCV] Implement assembler pseudo instructions for RV32I and RV64IAlex Bradbury2017-12-121-0/+138
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