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* [PowerPC] Support bd(n)zl and bd(n)zlrlUlrich Weigand2013-06-241-4/+10
| | | | | | | This adds support for the bd(n)zl and bd(n)zlrl instructions. The patterns are currently used for the asm parser only. llvm-svn: 184720
* [PowerPC] Support b(cond)l in the asm parserUlrich Weigand2013-06-241-24/+72
| | | | | | | This patch adds support for the conditional variants of bl. The pattern is currently used by the asm parser only. llvm-svn: 184719
* [PowerPC] Support blrl and variants in the asm parserUlrich Weigand2013-06-241-25/+50
| | | | | | | This patch adds support for blrl and its conditional variants. The patterns are (currently) used for the asm parser only. llvm-svn: 184718
* [PowerPC] Support R_PPC_REL16 family of relocationsUlrich Weigand2013-06-211-0/+26
| | | | | | | | | | | The GNU assembler supports (as extension to the ABI) use of PC-relative relocations in half16 fields, which allows writing code like: li 1, base-. This patch adds support for those relocation types in the assembler. llvm-svn: 184552
* [PowerPC] Support various tls-related modifiersUlrich Weigand2013-06-211-0/+129
| | | | | | | | | | The current code base only supports the minimum set of tls-related relocations and @modifiers that are necessary to support compiler- generated code. This patch extends this to the full set defined in the ABI (and supported by the GNU assembler) for the benefit of the assembler parser. llvm-svn: 184551
* [PowerPC] Support @higher et.al. modifiersUlrich Weigand2013-06-212-1/+29
| | | | | | | This adds support for the @higher, @highera, @highest, and @highesta modifers, including some missing relocation types. llvm-svn: 184550
* [PowerPC] Support @toc@h modifierUlrich Weigand2013-06-211-0/+5
| | | | | | | This adds the relocation type and other necessary infrastructure to use the @toc@h modifier in the assembler. llvm-svn: 184549
* [PowerPC] Support @h modifierUlrich Weigand2013-06-212-2/+17
| | | | | | | | | | | | This adds necessary infrastructure to support the @h modifier. Note that all required relocation types were already present (and unused). This patch provides support for using @h in the assembler; it would also be possible to now use this feature in code generated by the compiler, but this is not done yet. llvm-svn: 184548
* [MC] Support @ variants with directional labelsUlrich Weigand2013-06-201-1/+7
| | | | | | | | | | | The assembler parser common code supports recognizing symbol variants using the @ modifer. On PowerPC, it should also be possible to use (some of) those modifiers with directional labels, like "1f@l". This patch adds support for accepting symbol variants on directional labels as well. llvm-svn: 184437
* [PowerPC] Optimize @ha/@l constructsUlrich Weigand2013-06-201-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for having the assembler optimize fixups to constructs like "symbol@ha" or "symbol@l" if "symbol" can be resolved at assembler time. This optimization is already present in the PPCMCExpr.cpp code for handling PPC_HA16/PPC_LO16 target expressions. However, those target expression were used only on Darwin targets. This patch changes target expression code so that they are usable also with the GNU assembler (using the @ha / @l syntax instead of the ha16() / lo16() syntax), and changes the MCInst lowering code to generate those target expressions where appropriate. It also changes the asm parser to generate HA16/LO16 target expressions when parsing assembler source that uses the @ha / @l modifiers. The effect is that now the above- mentioned optimization automatically becomes available for those situations too. llvm-svn: 184436
* [PowerPC] Support compare mnemonics with implied CR0Ulrich Weigand2013-06-201-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just like for branch mnemonics (where support was recently added), the assembler is supposed to support extended mnemonics for the compare instructions where no condition register is specified explicitly (and CR0 is assumed implicitly). This patch adds support for those extended compare mnemonics. Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s =================================================================== --- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s +++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s @@ -449,21 +449,37 @@ # CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80] cmpdi 2, 3, 128 +# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80] + cmpdi 3, 128 # CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00] cmpd 2, 3, 4 +# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00] + cmpd 3, 4 # CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80] cmpldi 2, 3, 128 +# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80] + cmpldi 3, 128 # CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40] cmpld 2, 3, 4 +# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40] + cmpld 3, 4 # CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80] cmpwi 2, 3, 128 +# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80] + cmpwi 3, 128 # CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00] cmpw 2, 3, 4 +# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00] + cmpw 3, 4 # CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80] cmplwi 2, 3, 128 +# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80] + cmplwi 3, 128 # CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40] cmplw 2, 3, 4 +# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40] + cmplw 3, 4 # FIXME: Trap mnemonics Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td +++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td @@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>; defm : BranchExtendedMnemonic<"nu", 100>; defm : BranchExtendedMnemonic<"ns", 100>; +def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; +def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; +def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>; +def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; + llvm-svn: 184435
* [MC/DWARF] Support .debug_frame / .debug_line code alignment factorsUlrich Weigand2013-06-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | I've been comparing the object file output of LLVM's integrated assembler against the external assembler on PowerPC, and one area where differences still remain are in DWARF sections. In particular, the GNU assembler generates .debug_frame and .debug_line sections using a code alignment factor of 4, since all PowerPC instructions have size 4 and must be aligned to a multiple of 4. However, current MC code hard-codes a code alignment factor of 1. This patch changes this by adding a "minimum instruction alignment" data element to MCAsmInfo and using this as code alignment factor. This requires passing a MCContext into MCDwarfLineAddr::Encode and MCDwarfLineAddr::EncodeAdvanceLoc. Note that one caller, MCDwarfLineAddr::Write, didn't actually have that information available. However, it turns out that this routine is in fact never used in the whole code base, so the patch simply removes it. If it turns out to be needed again at a later time, it could be re-added with an updated interface. llvm-svn: 183834
* [PowerPC] Use assembler source in MC testsUlrich Weigand2013-06-126-155/+152
| | | | | | | | | | | A couple of old test cases in test/MC/PowerPC were still using LLVM IR. Now that we have a working assembler, we can move them to assembler tests instead: ppc64-initial-cfa.ll ppc64-relocs-01.ll ppc64-tls-relocs-01.ll llvm-svn: 183829
* [PowerPC] Support extended sc mnemonicUlrich Weigand2013-06-101-0/+2
| | | | | | | | | A plain "sc" without argument is supposed to be treated like "sc 0" by the assembler. This patch adds a corresponding alias. Problem reported by Joerg Sonnenberger. llvm-svn: 183687
* [PowerPC] Support branch mnemonics with implied CR0Ulrich Weigand2013-06-101-1/+197
| | | | | | | | | | The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
* Change how we iterate over relocations on ELF.Rafael Espindola2013-05-303-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | For COFF and MachO, sections semantically have relocations that apply to them. That is not the case on ELF. In relocatable objects (.o), a section with relocations in ELF has offsets to another section where the relocations should be applied. In dynamic objects and executables, relocations don't have an offset, they have a virtual address. The section sh_info may or may not point to another section, but that is not actually used for resolving the relocations. This patch exposes that in the ObjectFile API. It has the following advantages: * Most (all?) clients can handle this more efficiently. They will normally walk all relocations, so doing an effort to iterate in a particular order doesn't save time. * llvm-readobj now prints relocations in the same way the native readelf does. * probably most important, relocations that don't point to any section are now visible. This is the case of relocations in the rela.dyn section. See the updated relocation-executable.test for example. llvm-svn: 182908
* [PowerPC] Merge/rename PPC fixup typesUlrich Weigand2013-05-171-25/+25
| | | | | | | | | | | | | | Now that fixup_ppc_ha16 and fixup_ppc_lo16 are being treated exactly the same everywhere, it no longer makes sense to have two fixup types. This patch merges them both into a single type fixup_ppc_half16, and renames fixup_ppc_lo16_ds to fixup_ppc_half16ds for consistency. (The half16 and half16ds names are taken from the description of relocation types in the PowerPC ABI.) No change in code generation expected. llvm-svn: 182092
* [PowerPC] Fix processing of ha16/lo16 fixupsUlrich Weigand2013-05-172-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current PowerPC MC back end distinguishes between fixup_ppc_ha16 and fixup_ppc_lo16, which are determined by the instruction the fixup applies to, and uses this distinction to decide whether a fixup ought to resolve to the high or the low part of a symbol address. This isn't quite correct, however. It is valid -if unusual- assembler to use, e.g. li 1, symbol@ha or lis 1, symbol@l Whether the high or the low part of the address is used depends solely on the @ suffix, not on the instruction. In addition, both li 1, symbol and lis 1, symbol are valid, assuming the symbol address fits into 16 bits; again, both will then refer to the actual symbol value (so li will load the value itself, while lis will load the value shifted by 16). To fix this, two places need to be adapted. If the fixup cannot be resolved at assembler time, a relocation needs to be emitted via PPCELFObjectWriter::getRelocType. This routine already looks at the VK_ type to determine the relocation. The only problem is that will reject any _LO modifier in a ha16 fixup and vice versa. This is simply incorrect; any of those modifiers ought to be accepted for either fixup type. If the fixup *can* be resolved at assembler time, adjustFixupValue currently selects the high bits of the symbol value if the fixup type is ha16. Again, this is incorrect; see the above example lis 1, symbol Now, in theory we'd have to respect a VK_ modifier here. However, in fact common code never even attempts to resolve symbol references using any nontrivial VK_ modifier at assembler time; it will always fall back to emitting a reloc and letting the linker handle it. If this ever changes, presumably there'd have to be a target callback to resolve VK_ modifiers. We'd then have to handle @ha etc. there. llvm-svn: 182091
* [PowerPC] Remove need for adjustFixupOffst hackUlrich Weigand2013-05-151-42/+42
| | | | | | | | | | | | | | | | Now that applyFixup understands differently-sized fixups, we can define fixup_ppc_lo16/fixup_ppc_lo16_ds/fixup_ppc_ha16 to properly be 2-byte fixups, applied at an offset of 2 relative to the start of the instruction text. This has the benefit that if we actually need to generate a real relocation record, its address will come out correctly automatically, without having to fiddle with the offset in adjustFixupOffset. Tested on both 64-bit and 32-bit PowerPC, using external and integrated assembler. llvm-svn: 181894
* [PowerPC] Add test case for r181891Ulrich Weigand2013-05-151-0/+38
| | | | llvm-svn: 181892
* Implement the PowerPC system call (sc) instruction.Bill Schmidt2013-05-141-1/+2
| | | | | | Instruction added at request of Roman Divacky. Tested via asm-parser. llvm-svn: 181821
* [PowerPC] Add ELF relocation testsUlrich Weigand2013-05-081-0/+25
| | | | | | | | | This patch extends test/MC/PowerPC/ppc64-fixups.s to not only check for the correct fixup type in the --show-encoding output, but also runs the generated object file through llvm-readobj -r and verifies that the correct ELF relocation records were generated. llvm-svn: 181453
* [PowerPC] Parse platform-specifc variant kinds in AsmParserUlrich Weigand2013-05-031-0/+95
| | | | | | | | | This patch adds support for PowerPC platform-specific variant kinds in MCSymbolRefExpr::getVariantKindForName, and also adds a test case to verify they are translated to the appropriate fixup type. llvm-svn: 181053
* [PowerPC] Add some Book II instructions to AsmParserUlrich Weigand2013-05-031-0/+58
| | | | | | | | | | | | | This patch adds a couple of Book II instructions (isync, icbi) to the PowerPC assembler parser. These are needed when bootstrapping clang with the integrated assembler forced on, because they are used in inline asm statements in the code base. The test case adds the full list of Book II storage control instructions, including associated extended mnemonics. Again, those that are not yet supported as marked as FIXME. llvm-svn: 181052
* [PowerPC] Support extended mnemonics in AsmParserUlrich Weigand2013-05-031-0/+331
| | | | | | | | | | | | This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
* [PowerPC] Add assembler parserUlrich Weigand2013-05-035-0/+1294
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds assembler parser support to the PowerPC back end. The parser will run for any powerpc-*-* and powerpc64-*-* triples, but was tested only on 64-bit Linux. The supported syntax is intended to be compatible with the GNU assembler. The parser does not yet support all PowerPC instructions, but it does support anything that is generated by LLVM itself. There is no support for testing restricted instruction sets yet, i.e. the parser will always accept any instructions it knows, no matter what feature flags are given. Instruction operands will be checked for validity and errors generated. (Error handling in general could still be improved.) The patch adds a number of test cases to verify instruction and operand encodings. The tests currently cover all instructions from the following PowerPC ISA v2.06 Book I facilities: Branch, Fixed-point, Floating-Point, and Vector. Note that a number of these instructions are not yet supported by the back end; they are marked with FIXME. A number of follow-on check-ins will add extra features. When they are all included, LLVM passes all tests (including bootstrap) when using clang -cc1as as the system assembler. llvm-svn: 181050
* Replace coff-/elf-dump with llvm-readobjNico Rieck2013-04-123-110/+90
| | | | llvm-svn: 179361
* PowerPC: EH adjustmentsAdhemerval Zanella2013-01-091-3/+3
| | | | | | | | | This patch adjust the r171506 to make all DWARF enconding pc-relative for PPC64. It also adds the R_PPC64_REL32 relocation handling in MCJIT (since the eh_frame will not generate PIC-relative relocation) and also adds the emission of stubs created by the TTypeEncoding. llvm-svn: 171979
* PowerPC: Fix eh_frame relocation for PIC Adhemerval Zanella2013-01-041-33/+70
| | | | | | | | | This patch fixes the PPC eh_frame definitions for the personality and frame unwinding for PIC objects. It makes PIC build correctly creates relative relocations in the '.rela.eh_frame' segments and thus avoiding a text relocation that generates a DT_TEXTREL segments in link phase. llvm-svn: 171506
* Fix initial frame state on powerpc64.Ulrich Weigand2012-11-281-0/+41
| | | | | | | | | The createPPCMCAsmInfo routine used PPC::R1 as the initial frame pointer register, but on PPC64 the 32-bit R1 register does not have a corresponding DWARF number, causing invalid CIE initial frame state to be emitted. Fix by using PPC::X1 instead. llvm-svn: 168799
* This patch is in preparation for adding medium code model support to theBill Schmidt2012-11-141-1/+1
| | | | | | | | | | | | | | PPC64 target. The five tests modified herein test code generation that is sensitive to the code model selected. So I've added -code-model=small to the RUN commands for each. Since small code model is the default, this has no effect for now; but this prepares us for eventually changing the default to medium code model for PPC64. Test changes verified with small and medium code model as default on powerpc64-unknown-linux-gnu. All tests continue to pass. llvm-svn: 167999
* Add test case to verify correct relocs being generated forUlrich Weigand2012-11-131-0/+28
| | | | | | TLS symbols on PowerPC using the integrated assembler. llvm-svn: 167875
* Initial TOC support for PowerPC64 object creationAdhemerval Zanella2012-10-252-0/+71
This patch adds initial PPC64 TOC MC object creation using the small mcmodel (a single 64K TOC) adding the some TOC relocations (R_PPC64_TOC, R_PPC64_TOC16, and R_PPC64_TOC16DS). The addition of 'undefinedExplicitRelSym' hook on 'MCELFObjectTargetWriter' is meant to avoid the creation of an unreferenced ".TOC." symbol (used in the .odp creation) as well to set the R_PPC64_TOC relocation target as the temporary ".TOC." symbol. On PPC64 ABI, the R_PPC64_TOC relocation should not point to any symbol. llvm-svn: 166677
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