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* Allow exclamation and tilde to be parsed as a part of the ppc asm operand.Roman Divacky2014-03-121-0/+7
| | | | llvm-svn: 203699
* Try harder to evaluate expressions when printing assembly.Rafael Espindola2014-03-121-4/+8
| | | | | | | | | When printing assembly we don't have a Layout object, but we can still try to fold some constants. Testcase by Ulrich Weigand. llvm-svn: 203677
* Convert another llc -filetype=obj test.Rafael Espindola2013-10-281-0/+44
| | | | llvm-svn: 193548
* Convert another llc -filetype=obj test.Rafael Espindola2013-10-281-0/+61
| | | | llvm-svn: 193547
* Convert another llc -filetype=obj test.Rafael Espindola2013-10-281-0/+56
| | | | llvm-svn: 193546
* PPC: Allow partial fills in writeNopData()David Majnemer2013-09-261-1/+4
| | | | | | | | | | | | | | | | | | When asked to pad an irregular number of bytes, we should fill with zeros. This is consistent with the behavior specified in the AIX Assembler Language Reference as well as other LLVM and binutils assemblers. N.B. There is a small deviation from binutils' PPC assembler: when handling pads which are greater than 4 bytes but not mod 4, binutils will not emit any NOP sequences at all and only use zeros. This may or may not be a bug but there is no excellent rationale as to why that behavior is important to emulate. If that behavior is needed, we can change writeNopData() to behave in the same way. This fixes PR17352. llvm-svn: 191426
* PPC: Add support for fctid and fctiwDavid Majnemer2013-09-261-4/+8
| | | | | | | | | Encodings were checked against the Power ISA documents and double checked against binutils. This fixes PR17350. llvm-svn: 191419
* MC: Add support for treating $ as a reference to the PCDavid Majnemer2013-09-251-0/+5
| | | | | | | | | | | | | | | | | The binutils assembler supports a mode called DOLLAR_DOT which treats the dollar sign token as a reference to the current program counter if the dollar sign doesn't precede a constant or identifier. This commit adds a new MCAsmInfo flag stating whether or not a given target supports this interpretation of the dollar sign token; by default, this flag is not enabled. Further, enable this flag for PPC. The system assembler for AIX and binutils both support using the dollar sign in this manner. This fixes PR17353. llvm-svn: 191368
* Implement asm support for a few PowerPC bookIII that are needed for assemblingRoman Divacky2013-09-121-0/+107
| | | | | | FreeBSD kernel. llvm-svn: 190618
* Mark PPC MFTB and DST (and friends) as deprecatedHal Finkel2013-09-121-0/+12
| | | | | | | | Use the new instruction deprecation feature to mark mftb (now replaced with mfspr) and dst (along with the other Altivec cache control instructions) as deprecated when targeting cores supporting at least ISA v2.03. llvm-svn: 190605
* Given target assembler parsers a chance to handle variant expressionsJoerg Sonnenberger2013-08-272-0/+7
| | | | | | | first. Use this to turn the PPC modifiers into PPC specific expressions, allowing them to work on constants. llvm-svn: 189400
* Add the PPC fcpsgn instructionHal Finkel2013-08-191-2/+4
| | | | | | | | | Modern PPC cores support a floating-point copysign instruction, and we can use this to lower the FCOPYSIGN node (which is created from calls to the libm copysign function). A couple of extra patterns are necessary because the operand types of FCOPYSIGN need not agree. llvm-svn: 188653
* [tests] Cleanup initialization of test suffixes.Daniel Dunbar2013-08-161-2/+0
| | | | | | | | | | | | | | | | | - Instead of setting the suffixes in a bunch of places, just set one master list in the top-level config. We now only modify the suffix list in a few suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py). - Aside from removing the need for a bunch of lit.local.cfg files, this enables 4 tests that were inadvertently being skipped (one in Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been XFAILED). - This commit also fixes a bunch of config files to use config.root instead of older copy-pasted code. llvm-svn: 188513
* Fix FileCheck --check-prefix lines.Tim Northover2013-08-122-2/+2
| | | | | | | | | | Various tests had sprung up over the years which had --check-prefix=ABC on the RUN line, but "CHECK-ABC:" later on. This happened to work before, but was strictly incorrect. FileCheck is getting stricter soon though. Patch by Ron Ofir. llvm-svn: 188173
* [PowerPC] Revert r185476 and fix up TLS variant kindsUlrich Weigand2013-07-091-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the commit message to r185476 I wrote: >The PowerPC-specific modifiers VK_PPC_TLSGD and VK_PPC_TLSLD >correspond exactly to the generic modifiers VK_TLSGD and VK_TLSLD. >This causes some confusion with the asm parser, since VK_PPC_TLSGD >is output as @tlsgd, which is then read back in as VK_TLSGD. > >To avoid this confusion, this patch removes the PowerPC-specific >modifiers and uses the generic modifiers throughout. (The only >drawback is that the generic modifiers are printed in upper case >while the usual convention on PowerPC is to use lower-case modifiers. >But this is just a cosmetic issue.) This was unfortunately incorrect, there is is fact another, serious drawback to using the default VK_TLSLD/VK_TLSGD variant kinds: using these causes ELFObjectWriter::RelocNeedsGOT to return true, which in turn causes the ELFObjectWriter to emit an undefined reference to _GLOBAL_OFFSET_TABLE_. This is a problem on powerpc64, because it uses the TOC instead of the GOT, and the linker does not provide _GLOBAL_OFFSET_TABLE_, so the symbol remains undefined. This means shared libraries using TLS built with the integrated assembler are currently broken. While the whole RelocNeedsGOT / _GLOBAL_OFFSET_TABLE_ situation probably ought to be properly fixed at some point, for now I'm simply reverting the r185476 commit. Now this in turn exposes the breakage of handling @tlsgd/@tlsld in the asm parser that this check-in was originally intended to fix. To avoid this regression, I'm also adding a different fix for this problem: while common code now parses @tlsgd as VK_TLSGD, a special hack in the asm parser translates this code to the platform-specific VK_PPC_TLSGD that the back-end now expects. While this is not really pretty, it's self-contained and shouldn't hurt anything else for now. One the underlying problem is fixed, this hack can be reverted again. llvm-svn: 185945
* [PowerPC] Support ".machine any"Ulrich Weigand2013-07-091-0/+14
| | | | | | | | | | | | The PowerPC assembler is supposed to provide a directive .machine that allows switching the supported CPU instruction set on the fly. Since we do not yet check CPU feature sets at all and always accept any available instruction, this is not really useful at this point. However, it makes sense to accept (and ignore) ".machine any" to avoid spuriously rejecting existing assembler files that use this. llvm-svn: 185924
* [PowerPC] Support .llong and fix .wordUlrich Weigand2013-07-093-1/+57
| | | | | | | | This adds support for the .llong PowerPC-specifc assembler directive. In doing so, I notices that .word is currently incorrect: it is supposed to define a 2-byte data element, not a 4-byte one. llvm-svn: 185911
* [PowerPC] Support time base instructionsUlrich Weigand2013-07-081-0/+9
| | | | | | | | This adds support for the old-style time base instructions; while new programs are supposed to use mfspr, the mftb instructions are still supported and in use by existing assembler files. llvm-svn: 185829
* [PowerPC] Support basic compare mnemonicsUlrich Weigand2013-07-081-1/+19
| | | | | | | | | | | | | | | | | This adds support for the basic mnemoics (with the L operand) for the fixed-point compare instructions. These are defined as aliases for the already existing CMPW/CMPD patterns, depending on the value of L. This requires use of InstAlias patterns with immediate literal operands. To make this work, we need two further changes: - define a RegisterPrefix, because otherwise literals 0 and 1 would be parsed as literal register names - provide a PPCAsmParser::validateTargetOperandClass routine to recognize immediate literals (like ARM does) llvm-svn: 185826
* [PowerPC] Add some special @got@tprel fixup casesUlrich Weigand2013-07-051-0/+20
| | | | | | | | | | | | | | | When a target@got@tprel or target@got@tprel@l symbol variant is used in a fixup_ppc_half16 (*not* fixup_ppc_half16ds) context, we currently fail, since the corresponding R_PPC64_GOT_TPREL16 / R_PPC64_GOT_TPREL16_LO relocation types do not exist. However, since such symbol variants resolve to GOT offsets which are always 4-aligned, we can simply instead use the _DS variants of the relocation types, which *do* exist. The same applies for the @got@dtprel variants. llvm-svn: 185700
* [PowerPC] Make test case buildable with GNU asUlrich Weigand2013-07-051-12/+7
| | | | | | | | | | | The ppc64-fixups.s test currently fails to build with GNU as, since it does not support plain symbols as arguments to li/lis. Rewrite the test for R_PPC64_ADDR16 and R_PPC64_REL16 to use lwz instead. Allowing the test case to be built with both LLVM and GNU as makes it easier to spot unwanted difference in the output. llvm-svn: 185694
* [PowerPC] Support @tls in the asm parserUlrich Weigand2013-07-052-2/+15
| | | | | | | | | | | | | | | | | | This adds support for the last missing construct to parse TLS-related assembler code: add 3, 4, symbol@tls The ADD8TLS currently hard-codes the @tls into the assembler string. This cannot be handled by the asm parser, since @tls is parsed as a symbol variant. This patch changes ADD8TLS to have the @tls suffix printed as symbol variant on output too, which allows us to remove the isCodeGenOnly marker from ADD8TLS. This in turn means that we can add a AsmOperand to accept @tls marked symbols on input. As a side effect, this means that the fixup_ppc_tlsreg fixup type is no longer necessary and can be merged into fixup_ppc_nofixup. llvm-svn: 185692
* [PowerPC] Implement writeNopDataUlrich Weigand2013-07-041-0/+9
| | | | | | | | | | | This implements a proper PPCAsmBackend::writeNopData routine that actually writes PowerPC nop instructions. This fixes the last remaining difference in object file output (text section) between the integrated assembler and GNU as that I've seen anywhere. llvm-svn: 185662
* [PowerPC] Add all trap mnemonicsUlrich Weigand2013-07-042-2/+149
| | | | | | | This adds support for all basic and extended variants of the trap instructions to the asm parser. llvm-svn: 185638
* [PowerPC] Add asm parser support for CR expressionsUlrich Weigand2013-07-041-1/+99
| | | | | | | | This adds support for specifying condition registers and condition register fields via expressions using the symbols defined by the PowerISA, like "4*cr2+eq". llvm-svn: 185633
* [PowerPC] Support lmw/stmw in the asm parserUlrich Weigand2013-07-031-1/+6
| | | | | | | This adds support for the load/store multiple instructions, currently used by the asm parser only. llvm-svn: 185564
* [PowerPC] Use mtocrf when availableUlrich Weigand2013-07-032-4/+6
| | | | | | | | | | | | | | | | | | | | Just as with mfocrf, it is also preferable to use mtocrf instead of mtcrf when only a single CR register is to be written. Current code however always emits mtcrf. This probably does not matter when using an external assembler, since the GNU assembler will in fact automatically replace mtcrf with mtocrf when possible. It does create inefficient code with the integrated assembler, however. To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and uses those instead of MTCRF/MTCRF8 everything. Just as done in the MFOCRF patch committed as 185556, these patterns will be converted back to MTCRF if MTOCRF is not available on the machine. As a side effect, this allows to modify the MTCRF pattern to accept the full range of mask operands for the benefit of the asm parser. llvm-svn: 185561
* [PowerPC] Support mtspr/mfspr in the asm parserUlrich Weigand2013-07-032-4/+8
| | | | | | | | | This adds support for the generic forms of mtspr/mfspr for the asm parser. The compiler will continue to use the specialized patters for mtlr etc. since those are needed to correctly describe data flow. llvm-svn: 185532
* [PowerPC] PR16512 - Support TLS call sequences in the asm parserUlrich Weigand2013-07-021-0/+14
| | | | | | | | | This patch now adds support for recognizing TLS call sequences in the asm parser. This needs a new pattern BL8_TLS, which is like BL8_NOP_TLS except without nop. That pattern is used for the asm parser only. llvm-svn: 185478
* Cleanup PPC Altivec registers in CSR lists and improve VRSAVE handlingHal Finkel2013-07-021-0/+235
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a couple of (small) related changes here: 1. The printed name of the VRSAVE register has been changed from VRsave to vrsave in order to match the name accepted by GNU binutils. 2. Support for parsing vrsave has been added to the asm parser (it seems that there was no test case specifically covering this code, so I've added one). 3. The list of Altivec registers, which was common to all calling conventions, has been separated out. This allows us to define the base CSR lists, and then lists for each ABI with Altivec included. This allows SjLj, for example, to work correctly on non-Altivec targets without using unnatural definitions of the NoRegs CSR list. 4. VRSAVE is now always reserved on non-Darwin targets and all Altivec registers are reserved when Altivec is disabled. With these changes, it is now possible to compile a function containing __builtin_unwind_init() on Linux/PPC64 with debugging information. This did not work previously because GNU binutils assumes that all .cfi_offset offsets will be 8-byte aligned on PPC64 (and errors out if you provide a non-8-byte-aligned offset). This is not true for the vrsave register, however, because this register is used only on Darwin, GCC does not bother printing a .cfi_offset entry for it (even though there is a slot in the stack frame for it as specified by the ABI). This change allows us to do the same: we will also not print .cfi_offset directives for vrsave. llvm-svn: 185409
* [PowerPC] Add support for TLS data relocationsUlrich Weigand2013-07-011-2/+19
| | | | | | | | | | This adds support for TLS data relocations and modifiers: .quad target@dtpmod .quad target@tprel .quad target@dtprel Currently exploited by the asm parser only. llvm-svn: 185394
* [PowerPC] Support all condition register logical instructionsUlrich Weigand2013-07-012-7/+22
| | | | | | | This adds support for all missing condition register logical instructions and extended mnemonics to the asm parser. llvm-svn: 185387
* [PowerPC] Also add "msync" aliasUlrich Weigand2013-07-011-0/+2
| | | | | | | This adds an alias for "msync" (which is used on Book E systems instead of "sync"). llvm-svn: 185375
* [PowerPC] Fix @got references to local symbolsUlrich Weigand2013-07-011-0/+46
| | | | | | | | | | | A @got reference must always result in a relocation, so that the linker has a chance to set up the GOT entry, even if the symbol happens to be local. Add a PPCELFObjectWriter::ExplicitRelSym routine that enforces a relocation to be emitted for GOT references. llvm-svn: 185353
* [PowerPC] Add "wait" instructionUlrich Weigand2013-07-011-4/+8
| | | | | | This adds the "wait" instruction and its extended mnemonics. llvm-svn: 185350
* [PowerPC] Support "eieio" instructionUlrich Weigand2013-07-011-1/+2
| | | | | | | This adds support for the "eieio" instruction to the asm parser. llvm-svn: 185349
* [PowerPC] Add some existing instructions to ppc64-encoding-bookII.sUlrich Weigand2013-07-011-3/+8
| | | | | | | | | | The test case had a couple of FIXMEs where the instruction is in fact already supported by the back-end. In some other case, while the generic form of the instruction is not yet supported, a specialized form is. This adds tests for those already supported instructions / instruction forms. llvm-svn: 185347
* [PowerPC] Add variants of "sync" instructionUlrich Weigand2013-07-011-4/+7
| | | | | | | This adds support for the "sync $L" instruction with operand, and provides aliases for "lwsync" and "ptesync". llvm-svn: 185344
* [PowerPC] Accept 17-bit signed immediates for addisUlrich Weigand2013-06-262-0/+16
| | | | | | | | | | | | | | | | | | | The assembler currently strictly verifies that immediates for s16imm operands are in range (-32768 ... 32767). This matches the behaviour of the GNU assembler, with one exception: gas allows, as a special case, operands in an extended range (-65536 .. 65535) for the addis instruction only (and its extended mnemonic lis). The main reason for this seems to be to allow using unsigned 16-bit operands for lis, e.g. like lis %r1, 0xfedc. Since this has been supported by gas for a long time, and assembler source code seen "in the wild" actually exploits this feature, this patch adds equivalent support to LLVM for compatibility reasons. llvm-svn: 184946
* [PowerPC] Support symbolic u16imm operandsUlrich Weigand2013-06-261-0/+10
| | | | | | | | | | | | | | Currently, all instructions taking s16imm operands support symbolic operands. However, for u16imm operands, we only support actual immediate integers. This causes the assembler to reject code like ori %r5, %r5, symbol@l This patch changes the u16imm operand definition to likewise accept symbolic operands. In fact, s16imm and u16imm can share the same encoding routine, now renamed to getImm16Encoding. llvm-svn: 184944
* [PowerPC] Support @got modifierUlrich Weigand2013-06-251-0/+35
| | | | | | | Add VK_... values and relocation types necessary to support the @got family of modifiers. Used by the asm parser only. llvm-svn: 184860
* [PowerPC] Add extended rotate/shift mnemonicsUlrich Weigand2013-06-251-43/+85
| | | | | | This adds all missing extended rotate/shift mnemonics to the asm parser. llvm-svn: 184834
* [PowerPC] Add rldcr/rldic instructionsUlrich Weigand2013-06-251-4/+8
| | | | | | | | This adds pattern for the rldcr and rldic instructions (the last instruction from the rotate/shift family that were missing). They are currently used only by the asm parser. llvm-svn: 184833
* [PowerPC] Add extended subtract mnemonicsUlrich Weigand2013-06-251-1/+19
| | | | | | | | | | | | | | | This adds support for the extended subtract mnemonics to the asm parser: subi subis subic subic. sub sub. subc subc. llvm-svn: 184832
* [PowerPC] Support some miscellaneous mnemonics in the asm parserUlrich Weigand2013-06-241-5/+10
| | | | | | | | | | | This adds support for the following extended mnemonics: xnop mr. not not. la llvm-svn: 184767
* [PowerPC] Add some FIXMEsUlrich Weigand2013-06-241-0/+25
| | | | | | | A bunch of extendend mnemomics ought to support '.' forms. Add FIXMEs to the test case for those. llvm-svn: 184757
* [PowerPC] Add predicted forms of branchesUlrich Weigand2013-06-241-0/+1136
| | | | | | | | | | | | | | | | | | | | This adds support for the predicted forms of branches (+/-). There are three cases to consider: - Branches using a PPC::Predicate code For these, I've added new PPC::Predicate codes corresponding to the BO values for predicted branch forms, and updated insn printing to print them correctly. I've also added new aliases for the asm parser matching the new forms. - bt/bf I've added new aliases matching to gBC etc. - bd(n)z variants I've added new instruction patterns for the predicted forms. In all cases, the new patterns are used for the asm parser only. (The new infrastructure ought to be sufficient to allow use by the compiler too at some point.) llvm-svn: 184754
* [PowerPC] Add t/f branch mnemonics to asm parserUlrich Weigand2013-06-241-81/+107
| | | | | | | This adds the bt/bf/bd(n)zt/bd(n)zf mnemonics as aliases for the asm parser, resolving to the generic conditional patterns. llvm-svn: 184725
* [PowerPC] Support generic conditional branches in asm parserUlrich Weigand2013-06-241-9/+29
| | | | | | | | | | | This adds instruction patterns to cover the generic forms of the conditional branch instructions. This allows the assembler to support the generic mnemonics. The compiler will still generate the various specific forms of the instruction that were already supported. llvm-svn: 184722
* [PowerPC] Support absolute branchesUlrich Weigand2013-06-244-54/+197
| | | | | | | | | | | | | | | | | | There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
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