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* @l and friends adjust their value depending the context used in.Joerg Sonnenberger2014-08-102-5/+21
| | | | | | | For ori, they are unsigned, for addi, signed. Create a new target expression type to handle this and evaluate Fixups accordingly. llvm-svn: 215315
* Allow the third argument for the subi family to be an expression.Joerg Sonnenberger2014-08-091-3/+3
| | | | llvm-svn: 215286
* Use the full form of dccci and iccci from the early PPC 405 documents,Joerg Sonnenberger2014-08-091-6/+12
| | | | | | | since the operands are actually used on those cores. Provide aliases for the only documented case in the newer Power ISA speec. llvm-svn: 215282
* Allow large immediates for branch instructions in 32bit mode.Joerg Sonnenberger2014-08-081-0/+6
| | | | llvm-svn: 215240
* Add support for SPE load/store from memory.Joerg Sonnenberger2014-08-081-0/+157
| | | | llvm-svn: 215220
* Add the majority of the remaining SPE instructions.Joerg Sonnenberger2014-08-071-0/+415
| | | | llvm-svn: 215131
* IndentJoerg Sonnenberger2014-08-071-15/+15
| | | | llvm-svn: 215126
* Add mfasr and mtasrJoerg Sonnenberger2014-08-071-0/+7
| | | | llvm-svn: 215110
* Add mfrtcu and mfrtcl instructionsJoerg Sonnenberger2014-08-071-0/+6
| | | | llvm-svn: 215109
* Support mttbl and mttbu mnemonicJoerg Sonnenberger2014-08-071-0/+6
| | | | llvm-svn: 215108
* Add RFID instruction.Joerg Sonnenberger2014-08-071-0/+4
| | | | llvm-svn: 215105
* Add first bunch of SPE instructions. As they overlap with Altivec, markJoerg Sonnenberger2014-08-071-0/+50
| | | | | | | them as parser-only until the disassembler is extended to handle predicates properly. llvm-svn: 215102
* Add accessors for the PPC 403 bank registers.Joerg Sonnenberger2014-08-051-0/+49
| | | | llvm-svn: 214875
* Accessors for SSR2 and SSR3 on PPC 403.Joerg Sonnenberger2014-08-051-0/+13
| | | | llvm-svn: 214867
* Add dci/ici instructions for PPC 476 and friends.Joerg Sonnenberger2014-08-051-0/+7
| | | | llvm-svn: 214864
* Add mftblo and mftbhi for PPC 4xx.Joerg Sonnenberger2014-08-051-0/+13
| | | | llvm-svn: 214863
* Add lswi / stswi for assembler use with a warning to not add patternsJoerg Sonnenberger2014-08-051-0/+7
| | | | | | for them. llvm-svn: 214862
* Add TCR register accessJoerg Sonnenberger2014-08-041-0/+7
| | | | llvm-svn: 214826
* Add PPC 603's tlbld and tlbli instructions.Joerg Sonnenberger2014-08-041-0/+7
| | | | llvm-svn: 214825
* Add simplified aliases for access to DCCR, ICCR, DEAR and ESRJoerg Sonnenberger2014-08-041-0/+28
| | | | llvm-svn: 214797
* tlbre / tlbwe / tlbsx / tlbsx. variants for the PPC 4xx CPUs.Joerg Sonnenberger2014-08-041-0/+33
| | | | llvm-svn: 214784
* Recognize mftbl as alias for mftb, for symmetry with mttb.Joerg Sonnenberger2014-08-041-0/+3
| | | | llvm-svn: 214769
* Allow .lcomm with alignment on ELF targets.Joerg Sonnenberger2014-08-041-0/+22
| | | | llvm-svn: 214754
* Add support for m[ft][di]bat[ul] instructions.Joerg Sonnenberger2014-08-041-0/+102
| | | | llvm-svn: 214731
* Add features for PPC 4xx and e500/e500mc instructions.Joerg Sonnenberger2014-08-043-16/+22
| | | | | | Move the test cases for them into separate files. llvm-svn: 214724
* tlbia supportJoerg Sonnenberger2014-08-021-0/+4
| | | | llvm-svn: 214640
* mfdcr / mtdcr supportJoerg Sonnenberger2014-08-021-0/+8
| | | | llvm-svn: 214639
* Don't use additional arguments for dss and friends to satisfy DSS_Form,Joerg Sonnenberger2014-08-021-0/+20
| | | | | | | | | when let can do the same thing. Keep the 64bit variants as codegen-only. While they have a different register class, the encoding is the same for 32bit and 64bit mode. Having both present would otherwise confuse the disassembler. llvm-svn: 214636
* Add mtpid/mfpid for BookE.Joerg Sonnenberger2014-07-301-0/+6
| | | | llvm-svn: 214363
* Refactor TLBIVAX and add tlbsx.Joerg Sonnenberger2014-07-301-0/+3
| | | | llvm-svn: 214354
* Add rfdi and rfmci from the e500/e500mc ISA.Joerg Sonnenberger2014-07-301-0/+8
| | | | llvm-svn: 214339
* Add BookE's tlbre, tlbwe and tlbivax instructions.Joerg Sonnenberger2014-07-301-0/+10
| | | | llvm-svn: 214332
* Add BookE's wrtee and wrteei instructions.Joerg Sonnenberger2014-07-301-0/+12
| | | | llvm-svn: 214297
* SPRG 0 to 3 are valid outside BookE, so move them to the normal testJoerg Sonnenberger2014-07-302-47/+120
| | | | | | file. Add support for accessing SPRG 4 to 7 on BookE. llvm-svn: 214295
* Add rfci instruction.Joerg Sonnenberger2014-07-291-0/+3
| | | | llvm-svn: 214256
* mbar without argument is equivalent to mbar 0.Joerg Sonnenberger2014-07-291-0/+2
| | | | llvm-svn: 214250
* Recognize BookE's mbar instruction.Joerg Sonnenberger2014-07-291-0/+3
| | | | llvm-svn: 214244
* Fix typo in alias: DSIR -> DSISRJoerg Sonnenberger2014-07-291-2/+2
| | | | llvm-svn: 214238
* Support move to/from segment register.Joerg Sonnenberger2014-07-291-0/+14
| | | | llvm-svn: 214234
* Add a number of aliases for SPR access.Joerg Sonnenberger2014-07-291-0/+54
| | | | llvm-svn: 214196
* Add rfi instruction. Based on feedback by Ulrich Weigand.Joerg Sonnenberger2014-07-291-0/+3
| | | | llvm-svn: 214181
* [MC] Pass MCSymbolData to needsRelocateWithSymbolUlrich Weigand2014-07-201-0/+12
| | | | | | | | | | | | | | | | | | As discussed in a previous checking to support the .localentry directive on PowerPC, we need to inspect the actual target symbol in needsRelocateWithSymbol to make the appropriate decision based on that symbol's st_other bits. Currently, needsRelocateWithSymbol does not get the target symbol. However, it is directly available to its sole caller. This patch therefore simply extends the needsRelocateWithSymbol by a new parameter "const MCSymbolData &SD", passes in the target symbol, and updates all derived implementations. In particular, in the PowerPC implementation, this patch removes the FIXME added by the previous checkin. llvm-svn: 213487
* [PowerPC] ELFv2 MC support for .localentry directiveUlrich Weigand2014-07-203-0/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A second binutils feature needed to support ELFv2 is the .localentry directive. In the ELFv2 ABI, functions may have two entry points: one for calling the routine locally via "bl", and one for calling the function via function pointer (either at the source level, or implicitly via a PLT stub for global calls). The two entry points share a single ELF symbol, where the ELF symbol address identifies the global entry point address, while the local entry point is found by adding a delta offset to the symbol address. That offset is encoded into three platform-specific bits of the ELF symbol st_other field. The .localentry directive instructs the assembler to set those fields to encode a particular offset. This is typically used by a function prologue sequence like this: func: addis r2, r12, (.TOC.-func)@ha addi r2, r2, (.TOC.-func)@l .localentry func, .-func Note that according to the ABI, when calling the global entry point, r12 must be set to point the global entry point address itself; while when calling the local entry point, r2 must be set to point to the TOC base. The two instructions between the global and local entry point in the above example translate the first requirement into the second. This patch implements support in the PowerPC MC streamers to emit the .localentry directive (both into assembler and ELF object output), as well as support in the assembler parser to parse that directive. In addition, there is another change required in MC fixup/relocation handling to properly deal with relocations targeting function symbols with two entry points: When the target function is known local, the MC layer would immediately handle the fixup by inserting the target address -- this is wrong, since the call may need to go to the local entry point instead. The GNU assembler handles this case by *not* directly resolving fixups targeting functions with two entry points, but always emits the relocation and relies on the linker to handle this case correctly. This patch changes LLVM MC to do the same (this is done via the processFixupValue routine). Similarly, there are cases where the assembler would normally emit a relocation, but "simplify" it to a relocation targeting a *section* instead of the actual symbol. For the same reason as above, this may be wrong when the target symbol has two entry points. The GNU assembler again handles this case by not performing this simplification in that case, but leaving the relocation targeting the full symbol, which is then resolved by the linker. This patch changes LLVM MC to do the same (via the needsRelocateWithSymbol routine). NOTE: The method used in this patch is overly pessimistic, since the needsRelocateWithSymbol routine currently does not have access to the actual target symbol, and thus must always assume that it might have two entry points. This will be improved upon by a follow-on patch that modifies common code to pass the target symbol when calling needsRelocateWithSymbol. Reviewed by Hal Finkel. llvm-svn: 213485
* [PowerPC] ELFv2 MC support for .abiversion directiveUlrich Weigand2014-07-201-0/+9
| | | | | | | | | | | | | ELFv2 binaries are marked by a bit in the ELF header e_flags field. A new assembler directive .abiversion can be used to set that flag. This patch implements support in the PowerPC MC streamers to emit the .abiversion directive (both into assembler and ELF binary output), as well as support in the assembler parser to parse the .abiversion directive. Reviewed by Hal Finkel. llvm-svn: 213484
* [PowerPC] 32-bit ELF PIC supportHal Finkel2014-07-181-0/+17
| | | | | | | | | | This adds initial support for PPC32 ELF PIC (Position Independent Code; the -fPIC variety), thus rectifying a long-standing deficiency in the PowerPC backend. Patch by Justin Hibbits! llvm-svn: 213427
* Emit DWARF3 call frame information when DWARF3+ debug info is requestedOliver Stannard2014-06-191-4/+4
| | | | | | | | | | | | | | | | Currently, llvm always emits a DWARF CIE with a version of 1, even when emitting DWARF 3 or 4, which both support CIE version 3. This patch makes it emit the newer CIE version when we are emitting DWARF 3 or 4. This will not reduce compatibility, as we already emit other DWARF3/4 features, and is worth doing as the DWARF3 spec removed some ambiguities in the interpretation of call frame information. It also fixes a minor bug where the "return address" field of the CIE was encoded as a ULEB128, which is only valid when the CIE version is 3. There are no test changes for this, because (as far as I can tell) none of the platforms that we test have a return address register with a DWARF register number >127. llvm-svn: 211272
* Reduce verbiage of lit.local.cfg filesAlp Toker2014-06-091-2/+1
| | | | | | We can just split targets_to_build in one place and make it immutable. llvm-svn: 210496
* [MC] Emit an error if cfi_startproc is used before a symbol is defined.Quentin Colombet2014-04-151-0/+1
| | | | | | | | | Currently, we bind those directives with the last symbol, so if none has been defined, this would lead to a crash of the compiler. <rdar://problem/15939159> llvm-svn: 206236
* [PowerPC] Generate little-endian object filesUlrich Weigand2014-03-2419-4277/+6574
| | | | | | | | | | | | | | | | | | | | As a first step towards real little-endian code generation, this patch changes the PowerPC MC layer to actually generate little-endian object files. This involves passing the little-endian flag through the various layers, including down to createELFObjectWriter so we actually get basic little-endian ELF objects, emitting instructions in little-endian order, and handling fixups and relocations as appropriate for little-endian. The bulk of the patch is to update most test cases in test/MC/PowerPC to verify both big- and little-endian encodings. (The only test cases *not* updated are those that create actual big-endian ABI code, like the TLS tests.) Note that while the object files are now little-endian, the generated code itself is not yet updated, in particular, it still does not adhere to the ELFv2 ABI. llvm-svn: 204634
* [PowerPC] Initial support for the VSX instruction setHal Finkel2014-03-131-0/+298
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | VSX is an ISA extension supported on the POWER7 and later cores that enhances floating-point vector and scalar capabilities. Among other things, this adds <2 x double> support and generally helps to reduce register pressure. The interesting part of this ISA feature is the register configuration: there are 64 new 128-bit vector registers, the 32 of which are super-registers of the existing 32 scalar floating-point registers, and the second 32 of which overlap with the 32 Altivec vector registers. This makes things like vector insertion and extraction tricky: this can be free but only if we force a restriction to the right register subclass when needed. A new "minipass" PPCVSXCopy takes care of this (although it could do a more-optimal job of it; see the comment about unnecessary copies below). Please note that, currently, VSX is not enabled by default when targeting anything because it is not yet ready for that. The assembler and disassembler are fully implemented and tested. However: - CodeGen support causes miscompiles; test-suite runtime failures: MultiSource/Benchmarks/FreeBench/distray/distray MultiSource/Benchmarks/McCat/08-main/main MultiSource/Benchmarks/Olden/voronoi/voronoi MultiSource/Benchmarks/mafft/pairlocalalign MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4 SingleSource/Benchmarks/CoyoteBench/almabench SingleSource/Benchmarks/Misc/matmul_f64_4x4 - The lowering currently falls back to using Altivec instructions far more than it should. Worse, there are some things that are scalarized through the stack that shouldn't be. - A lot of unnecessary copies make it past the optimizers, and this needs to be fixed. - Many more regression tests are needed. Normally, I'd fix these things prior to committing, but there are some students and other contributors who would like to work this, and so it makes sense to move this development process upstream where it can be subject to the regular code-review procedures. llvm-svn: 203768
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