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* Add aliases for mfvrsave/mtvrsave.Eric Christopher2016-06-091-0/+6
| | | | | | | Update a test as we're now going to emit it for easier reading of generated assembly as well. llvm-svn: 272339
* This reverts commit r265505.Kit Barton2016-04-281-9/+0
| | | | | | | Revert "[Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random number, set bool, and dfp test significance". This patch has caused a functional regression in SPEC2k6 namd, and a performance regression in mesa-pipe. llvm-svn: 267927
* [Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random ↵Chuang-Yu Cheng2016-04-061-0/+9
| | | | | | | | | | | | | | | | | | | | | number, set bool, and dfp test significance This patch implement the following instructions: - addpcis subpcis - maddhd maddhdu maddld - modsw moduw modsd modud - darn - extswsli extswsli. - setb - dtstsfi dtstsfiq Total 15 instructions Reviewers: nemanjai hfinkel tjablin amehsan kbarton http://reviews.llvm.org/D17885 llvm-svn: 265505
* [Power9] Implement copy-paste, msgsync, slb, and stop instructionsChuang-Yu Cheng2016-04-061-0/+13
| | | | | | | | | | | | | This patch implements the following BookII and Book III instructions: - copy copy_first cp_abort paste paste. paste_last - msgsync - slbieg slbsync - stop Total 10 instructions Reviewers: nemanjai hfinkel tjablin amehsan kbarton llvm-svn: 265504
* [PowerPC] Enable printing instructions using aliasesHal Finkel2015-04-231-390/+390
| | | | | | | | | | | TableGen had been nicely generating code to print a number of instructions using shorter aliases (and PowerPC has plenty of short mnemonics), but we were not calling it. For some of the aliases we support in the parser, TableGen can't infer the "inverse" alias relationship, so there is still more to do. Thus, after some hours of updating test cases... llvm-svn: 235616
* [PowerPC] Add asm support for cache-inhibited ld/st instructionsHal Finkel2014-11-301-0/+27
| | | | | | | | | Add assembler support for the fixed-point cache-inhibited load/store instructions. These are hypervisor-level only, so don't get too excited ;) Fixes PR21650. llvm-svn: 222976
* [PowerPC] Add the 'attn' instructionHal Finkel2014-11-251-0/+6
| | | | | | | | The attn instruction is not part of the Power ISA, but is documented in the A2 user manual, and is accepted by the GNU assembler for the A2 and the POWER4+. Reported as part of PR21650. llvm-svn: 222712
* Add mfasr and mtasrJoerg Sonnenberger2014-08-071-0/+7
| | | | llvm-svn: 215110
* Add mfrtcu and mfrtcl instructionsJoerg Sonnenberger2014-08-071-0/+6
| | | | llvm-svn: 215109
* Add RFID instruction.Joerg Sonnenberger2014-08-071-0/+4
| | | | llvm-svn: 215105
* Add lswi / stswi for assembler use with a warning to not add patternsJoerg Sonnenberger2014-08-051-0/+7
| | | | | | for them. llvm-svn: 214862
* Add features for PPC 4xx and e500/e500mc instructions.Joerg Sonnenberger2014-08-041-16/+0
| | | | | | Move the test cases for them into separate files. llvm-svn: 214724
* tlbia supportJoerg Sonnenberger2014-08-021-0/+4
| | | | llvm-svn: 214640
* mfdcr / mtdcr supportJoerg Sonnenberger2014-08-021-0/+8
| | | | llvm-svn: 214639
* Don't use additional arguments for dss and friends to satisfy DSS_Form,Joerg Sonnenberger2014-08-021-0/+20
| | | | | | | | | when let can do the same thing. Keep the 64bit variants as codegen-only. While they have a different register class, the encoding is the same for 32bit and 64bit mode. Having both present would otherwise confuse the disassembler. llvm-svn: 214636
* Add mtpid/mfpid for BookE.Joerg Sonnenberger2014-07-301-0/+6
| | | | llvm-svn: 214363
* Add rfdi and rfmci from the e500/e500mc ISA.Joerg Sonnenberger2014-07-301-0/+8
| | | | llvm-svn: 214339
* SPRG 0 to 3 are valid outside BookE, so move them to the normal testJoerg Sonnenberger2014-07-301-0/+60
| | | | | | file. Add support for accessing SPRG 4 to 7 on BookE. llvm-svn: 214295
* Fix typo in alias: DSIR -> DSISRJoerg Sonnenberger2014-07-291-2/+2
| | | | llvm-svn: 214238
* Add a number of aliases for SPR access.Joerg Sonnenberger2014-07-291-0/+54
| | | | llvm-svn: 214196
* [PowerPC] Generate little-endian object filesUlrich Weigand2014-03-241-2198/+3438
| | | | | | | | | | | | | | | | | | | | As a first step towards real little-endian code generation, this patch changes the PowerPC MC layer to actually generate little-endian object files. This involves passing the little-endian flag through the various layers, including down to createELFObjectWriter so we actually get basic little-endian ELF objects, emitting instructions in little-endian order, and handling fixups and relocations as appropriate for little-endian. The bulk of the patch is to update most test cases in test/MC/PowerPC to verify both big- and little-endian encodings. (The only test cases *not* updated are those that create actual big-endian ABI code, like the TLS tests.) Note that while the object files are now little-endian, the generated code itself is not yet updated, in particular, it still does not adhere to the ELFv2 ABI. llvm-svn: 204634
* [PowerPC] Add all trap mnemonicsUlrich Weigand2013-07-041-1/+139
| | | | | | | This adds support for all basic and extended variants of the trap instructions to the asm parser. llvm-svn: 185638
* [PowerPC] Add asm parser support for CR expressionsUlrich Weigand2013-07-041-1/+99
| | | | | | | | This adds support for specifying condition registers and condition register fields via expressions using the symbols defined by the PowerISA, like "4*cr2+eq". llvm-svn: 185633
* [PowerPC] Use mtocrf when availableUlrich Weigand2013-07-031-0/+2
| | | | | | | | | | | | | | | | | | | | Just as with mfocrf, it is also preferable to use mtocrf instead of mtcrf when only a single CR register is to be written. Current code however always emits mtcrf. This probably does not matter when using an external assembler, since the GNU assembler will in fact automatically replace mtcrf with mtocrf when possible. It does create inefficient code with the integrated assembler, however. To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and uses those instead of MTCRF/MTCRF8 everything. Just as done in the MFOCRF patch committed as 185556, these patterns will be converted back to MTCRF if MTOCRF is not available on the machine. As a side effect, this allows to modify the MTCRF pattern to accept the full range of mask operands for the benefit of the asm parser. llvm-svn: 185561
* [PowerPC] Support mtspr/mfspr in the asm parserUlrich Weigand2013-07-031-2/+4
| | | | | | | | | This adds support for the generic forms of mtspr/mfspr for the asm parser. The compiler will continue to use the specialized patters for mtlr etc. since those are needed to correctly describe data flow. llvm-svn: 185532
* [PowerPC] Support all condition register logical instructionsUlrich Weigand2013-07-011-1/+10
| | | | | | | This adds support for all missing condition register logical instructions and extended mnemonics to the asm parser. llvm-svn: 185387
* [PowerPC] Add extended rotate/shift mnemonicsUlrich Weigand2013-06-251-43/+85
| | | | | | This adds all missing extended rotate/shift mnemonics to the asm parser. llvm-svn: 184834
* [PowerPC] Add extended subtract mnemonicsUlrich Weigand2013-06-251-1/+19
| | | | | | | | | | | | | | | This adds support for the extended subtract mnemonics to the asm parser: subi subis subic subic. sub sub. subc subc. llvm-svn: 184832
* [PowerPC] Support some miscellaneous mnemonics in the asm parserUlrich Weigand2013-06-241-5/+10
| | | | | | | | | | | This adds support for the following extended mnemonics: xnop mr. not not. la llvm-svn: 184767
* [PowerPC] Add some FIXMEsUlrich Weigand2013-06-241-0/+25
| | | | | | | A bunch of extendend mnemomics ought to support '.' forms. Add FIXMEs to the test case for those. llvm-svn: 184757
* [PowerPC] Add predicted forms of branchesUlrich Weigand2013-06-241-0/+1136
| | | | | | | | | | | | | | | | | | | | This adds support for the predicted forms of branches (+/-). There are three cases to consider: - Branches using a PPC::Predicate code For these, I've added new PPC::Predicate codes corresponding to the BO values for predicted branch forms, and updated insn printing to print them correctly. I've also added new aliases for the asm parser matching the new forms. - bt/bf I've added new aliases matching to gBC etc. - bd(n)z variants I've added new instruction patterns for the predicted forms. In all cases, the new patterns are used for the asm parser only. (The new infrastructure ought to be sufficient to allow use by the compiler too at some point.) llvm-svn: 184754
* [PowerPC] Add t/f branch mnemonics to asm parserUlrich Weigand2013-06-241-81/+107
| | | | | | | This adds the bt/bf/bd(n)zt/bd(n)zf mnemonics as aliases for the asm parser, resolving to the generic conditional patterns. llvm-svn: 184725
* [PowerPC] Support absolute branchesUlrich Weigand2013-06-241-52/+156
| | | | | | | | | | | | | | | | | | There is currently only limited support for the "absolute" variants of branch instructions. This patch adds support for the absolute variants of all branches that are currently otherwise supported. This requires adding new fixup types so that the correct variant of relocation type can be selected by the object writer. While the compiler will continue to usually choose the relative branch variants, this will allow the asm parser to fully support the absolute branches, with either immediate (numerical) or symbolic target addresses. No change in code generation intended. llvm-svn: 184721
* [PowerPC] Support bd(n)zl and bd(n)zlrlUlrich Weigand2013-06-241-4/+10
| | | | | | | This adds support for the bd(n)zl and bd(n)zlrl instructions. The patterns are currently used for the asm parser only. llvm-svn: 184720
* [PowerPC] Support b(cond)l in the asm parserUlrich Weigand2013-06-241-24/+72
| | | | | | | This patch adds support for the conditional variants of bl. The pattern is currently used by the asm parser only. llvm-svn: 184719
* [PowerPC] Support blrl and variants in the asm parserUlrich Weigand2013-06-241-25/+50
| | | | | | | This patch adds support for blrl and its conditional variants. The patterns are (currently) used for the asm parser only. llvm-svn: 184718
* [PowerPC] Support compare mnemonics with implied CR0Ulrich Weigand2013-06-201-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just like for branch mnemonics (where support was recently added), the assembler is supposed to support extended mnemonics for the compare instructions where no condition register is specified explicitly (and CR0 is assumed implicitly). This patch adds support for those extended compare mnemonics. Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s =================================================================== --- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s +++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s @@ -449,21 +449,37 @@ # CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80] cmpdi 2, 3, 128 +# CHECK: cmpdi 0, 3, 128 # encoding: [0x2c,0x23,0x00,0x80] + cmpdi 3, 128 # CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00] cmpd 2, 3, 4 +# CHECK: cmpd 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x00] + cmpd 3, 4 # CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80] cmpldi 2, 3, 128 +# CHECK: cmpldi 0, 3, 128 # encoding: [0x28,0x23,0x00,0x80] + cmpldi 3, 128 # CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40] cmpld 2, 3, 4 +# CHECK: cmpld 0, 3, 4 # encoding: [0x7c,0x23,0x20,0x40] + cmpld 3, 4 # CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80] cmpwi 2, 3, 128 +# CHECK: cmpwi 0, 3, 128 # encoding: [0x2c,0x03,0x00,0x80] + cmpwi 3, 128 # CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00] cmpw 2, 3, 4 +# CHECK: cmpw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x00] + cmpw 3, 4 # CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80] cmplwi 2, 3, 128 +# CHECK: cmplwi 0, 3, 128 # encoding: [0x28,0x03,0x00,0x80] + cmplwi 3, 128 # CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40] cmplw 2, 3, 4 +# CHECK: cmplw 0, 3, 4 # encoding: [0x7c,0x03,0x20,0x40] + cmplw 3, 4 # FIXME: Trap mnemonics Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td +++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td @@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>; defm : BranchExtendedMnemonic<"nu", 100>; defm : BranchExtendedMnemonic<"ns", 100>; +def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; +def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; +def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>; +def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; +def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>; +def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; + llvm-svn: 184435
* [PowerPC] Support branch mnemonics with implied CR0Ulrich Weigand2013-06-101-1/+197
| | | | | | | | | | The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
* [PowerPC] Support extended mnemonics in AsmParserUlrich Weigand2013-05-031-0/+331
This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. llvm-svn: 181051
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