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* [mips][msa] Fix definition of SLD instruction.Matheus Almeida2013-10-211-12/+12
| | | | | | | The second parameter of the SLD intrinsic is the number of columns (GPR) to slide left the source array. llvm-svn: 193076
* [mips][msa] Direct Object Emission support for BIT instructions.Matheus Almeida2013-10-141-0/+150
| | | | | | | | | | | | | | | | | | List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
* [mips][msa] Direct Object Emission support for VEC instructions.Matheus Almeida2013-10-141-0/+27
| | | | | | | List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
* [mips][msa] Direct Object Emission of INSVE.{b,h,w,d}.Matheus Almeida2013-10-141-0/+18
| | | | llvm-svn: 192587
* [mips][msa] Direct Object Emission for the majority of the ELM instructions.Matheus Almeida2013-10-141-0/+48
| | | | | | | | | | List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
* [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.Matheus Almeida2013-10-141-0/+15
| | | | | | | | | INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. This happens because MSA registers may be suffixed by an index in the form of an immediate or a general purpose register. The changes to parseMSARegs reflect that requirement. llvm-svn: 192582
* This reverts 192447 because of compiler warning generated on darwin build.Matheus Almeida2013-10-111-15/+0
| | | | llvm-svn: 192451
* This reverts r192449 because of compiler warning generated on darwin build.Matheus Almeida2013-10-111-48/+0
| | | | llvm-svn: 192450
* [mips][msa] Direct Object Emission for the majority of the ELM instructions.Matheus Almeida2013-10-111-0/+48
| | | | llvm-svn: 192449
* [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.Matheus Almeida2013-10-111-0/+15
| | | | | | | | INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. This happens because MSA registers may be suffixed by an index in the form of an immediate or a general purpose register. The changes to parseMSARegs reflect that requirement. llvm-svn: 192447
* [mips][msa] Direct Object Emission for I8 instructions.Jack Carter2013-09-301-0/+36
| | | | | | | | | This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b. Patch by Matheus Almeida llvm-svn: 191688
* [mips][msa] Direct Object Emission for I5 instructions.Jack Carter2013-09-301-0/+138
| | | | | | | | | This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
* [mips][msa] Direct Object Emission for 2R instructions.Jack Carter2013-09-301-0/+36
| | | | | | | | | This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}. Patch by Matheus Almeida llvm-svn: 191685
* [PATCH 1/4] [mips][msa] Source register of FILL instructions is GPRJack Carter2013-09-301-0/+15
| | | | | | | | and not an MSA register Patch by Matheus Almeida llvm-svn: 191684
* [mips][msa] Direct Object Emission for 3RF instructions.Jack Carter2013-09-261-0/+252
| | | | | | Patch by Matheus Almeida llvm-svn: 191461
* [mips][msa] Direct Object Emission for 3R instructions.Jack Carter2013-09-261-0/+720
| | | | | | | | This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
* [mips][msa] Direct Object Emission for 2RF instructions.Jack Carter2013-09-251-0/+90
| | | | | | Patch by Matheus Almeida llvm-svn: 191413
* [mips][msa] Direct Object Emission support for the MSA instruction set. Jack Carter2013-09-251-0/+12
In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions. Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function). Patch by Matheus Almeida llvm-svn: 191412
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