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* [mips] Marked up instructions added in MIPS-II and tested that IAS for ↵Daniel Sanders2014-05-082-0/+37
| | | | | | | | | | | | | | | | | | | -mcpu=mips1 does not accept them Summary: A small number of instructions are rejected with the wrong error message. These have been placed in a separate test for now. There seems to be some parsing quirk that triggers when these instructions are disabled. Depends on D3571 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3647 llvm-svn: 208305
* [mips] Implement tlbp, tlbr, tlbwi, and tlbwrDaniel Sanders2014-05-082-4/+4
| | | | | | | | | | Reviewers: vmedic, dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3571 llvm-svn: 208301
* [mips] Add highly experimental support for MIPS-I, MIPS-II, MIPS-III, and MIPS-VDaniel Sanders2014-05-072-4/+2
| | | | | | | | | | | | | | | | | | | | Summary: These processors will only be available for the integrated assembler at first (CodeGen will emit a fatal error saying they are not implemented). The intention is to work through the existing instructions and correctly annotate the ISA they were added in so that we have a sufficiently good base to start MIPS64r6 development. MIPS64r6 removes/re-encodes certain instructions and I believe it is best to define ISA's using set-union's as far as possible rather than using set-subtraction. Reviewers: vmedic Subscribers: emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D3569 llvm-svn: 208221
* [mips] Removed two-operand alias for sllv, sr[al]v, rotrv, dsllv, dsr[al]v, ↵Daniel Sanders2014-05-011-3/+0
| | | | | | | | | | and drotrv GAS doesn't actually accept these particular cases. The mnemonic without the trailing 'v' still supports two-operand aliases. llvm-svn: 207740
* [mips] Add instruction alias (negu).Matheus Almeida2014-04-301-0/+2
| | | | | | | | | | | | Summary: negu $reg is equivalent to negu $reg, $reg. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3510 llvm-svn: 207673
* [mips] Add instruction alias (sltu).Matheus Almeida2014-04-301-0/+1
| | | | | | | | | | | | | | Summary: The pattern sltu $r1, $r2, $imm is found in handwritten assembly which is just a shorthand version of sltui $r1, $r2, $imm. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3508 llvm-svn: 207671
* [mips] Add instruction alias (sll and srl).Matheus Almeida2014-04-301-0/+2
| | | | | | | | | | | | | | Summary: The pattern sll/srl $rd, $rt, $rs is found in handwritten assembly which is just a shorthand version of sllv/srlv $rd, $rt, $rs. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3483 llvm-svn: 207657
* [mips] Update tests with encoding information for slt, slti, sltiu and sltu.Matheus Almeida2014-04-301-4/+4
| | | | | | | | | | | | | | Summary: Also renamed non-portable register names (e.g. $t2) so that we don't end up with a different encoding for what appears to be an equivalent instruction. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3505 llvm-svn: 207655
* [mips] Use TwoOperandAliasConstraint for shift instructions.Matheus Almeida2014-04-161-4/+13
| | | | | | | | | | This enables TableGen to generate an additional two operand matcher for our shift_rotate_imm and shift_rotate_reg class of instructions. The tests were also updated so that they include now encoding information for all affected instructions. llvm-svn: 206398
* [mips] Implement ehb, ssnop, and pause in assemblerDaniel Sanders2014-04-032-2/+2
| | | | | | | | | | | | Summary: Add negative tests for pause Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3246 llvm-svn: 205537
* [mips] Added a full set of instruction test cases for all ISA's (but not ASE's).Daniel Sanders2014-03-312-0/+102
Summary: Where those ISA's are not currently supported, the test is run with the smallest superset of that ISA. Some instructions are valid but don't pass yet. These have been placed in the valid-xfail.s's which will XPASS if _any_ instruction starts working. The valid.s's do not verify the encoding yet. There are also no tests checking that instructions from neighbouring ISA's are not accepted. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3214 llvm-svn: 205180
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