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* [X86][Disassembler] Clamp index to 4-bits when decoding GPR registers.Craig Topper2018-06-011-1/+1
| | | | | | A 5-bit value can occur when EVEX.X is 0 due to it being used to extend modrm.rm to encode XMM16-31. But if modrm.rm instead encodes a GPR, the Intel documentation says EVEX.X should be ignored so just mask it to 4 bits once we know its a GPR. llvm-svn: 333725
* [X86] Add a test case showing a bad disassembling of an EVEX instruction ↵Craig Topper2018-06-011-0/+3
| | | | | | | | with EVEX.X=0 and a GPR encoded in modrm.rm. EVEX.X is used to extended modrm.rm when the instruction encodes a XMM/YMM/ZMM register. But we aren't properly ignoring it when it encodes a GPR and we end up printing whatever registers exist in X86 register enum after the GPRs. llvm-svn: 333724
* [X86][Disassembler] Make sure EVEX.X is not used to extend base registers of ↵Craig Topper2018-06-011-0/+4
| | | | | | | | | | memory operations. This was an accidental side effect of EVEX.X being used to encode XMM16-XMM31 using modrm.rm with modrm.mod==0x3. I think there are still more bugs related to this. llvm-svn: 333722
* [X86] Make sure the check for VEX.vvvv being all ones on instructions that ↵Craig Topper2018-06-011-0/+4
| | | | | | don't use it doesn't ignore a bit in 32-bit mode. llvm-svn: 333717
* [X86][Disassembler] Suppress reading of EVEX.V' and EVEX.R' in 32-bit mode.Craig Topper2018-06-011-2/+2
| | | | llvm-svn: 333714
* [X86] Add test cases showing the disassembler producing an xmm16-xmm31 ↵Craig Topper2018-06-011-0/+6
| | | | | | | | register in 32-bit mode. We aren't properly suppressing the reading of VEX.R' and VEX.V' in 32-bit mode. llvm-svn: 333713
* [mips] Correct the predicates of arithmetic and logic instructions.Simon Dardis2018-05-303-4/+9
| | | | | | | | | | | | As part of this effort, duplicate and correct the predicates of some aliases. Also disable code generation of some short form instructions for FastISel, as it would otherwise reject them. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D47075 llvm-svn: 333530
* [mips] Correct the predicates for a number of instructions.Simon Dardis2018-05-292-4/+4
| | | | | | | | | | Previously, their listed predicates were overridden at the scope level. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46947 llvm-svn: 333405
* [mips] Add microMIPSR6 ll/sc instructions.Simon Dardis2018-05-201-0/+4
| | | | | | | | | | Previously the compiler was using the microMIPSR3 variants, incorrectly. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46948 llvm-svn: 332820
* [mips] Add support for Global INValidate ASEPetar Jovanovic2018-05-174-0/+20
| | | | | | | | | | | | | | | | | | This includes Instructions: ginvi, ginvt, Assembler directives: .set ginv, .set noginv, .module ginv, .module noginv Attribute: ginv .MIPS.abiflags: GINV (0x20000) Patch by Vladimir Stefanovic. Differential Revision: https://reviews.llvm.org/D46268 llvm-svn: 332624
* AMDGPU: Fix v_dot{4, 8}* instruction encodingKonstantin Zhuravlyov2018-05-151-8/+308
| | | | | | Differential Revision: https://reviews.llvm.org/D46848 llvm-svn: 332387
* AMDGPU: Add disasm tests for deep learning instructions + fix v_fmac_f32 disasmKonstantin Zhuravlyov2018-05-151-0/+973
| | | | | | Differential Revision: https://reviews.llvm.org/D46853 llvm-svn: 332377
* [mips] Add disassembly support for comparison instructionsSimon Dardis2018-05-151-0/+32
| | | | llvm-svn: 332340
* [mips] Fix predicates of mfc1, mtc1 instructionsSimon Dardis2018-05-154-0/+16
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46692 llvm-svn: 332339
* [mips] Fix the predicates of round, ceiling, floor and trunc.Simon Dardis2018-05-142-0/+20
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46691 llvm-svn: 332258
* [mips] Correct the predicates of indexed floating point stores and loads.Simon Dardis2018-05-142-0/+4
| | | | | | | | | | Also, fix the register class for microMIPS. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46689 llvm-svn: 332227
* [mips] Enable disassembly of fused (negative) multiply add/sub instructionsSimon Dardis2018-05-112-0/+16
| | | | | | | | Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46392 llvm-svn: 332097
* [WebAssembly] Initial Disassembler.Sam Clegg2018-05-102-0/+36
| | | | | | | | | | | | | | | | | | | | | This implements a new table-gen emitter to create tables for a wasm disassembler, and a dissassembler to use them. Comes with 2 tests, that tests a few instructions manually. Is also able to disassemble large .wasm files with objdump reasonably. Not working so well, to be addressed in followups: - objdump appears to be passing an incorrect starting point. - since the disassembler works an instruction at a time, and it is disassembling stack instruction, it has no idea of pseudo register assignments. These registers are required for the instruction printing code that follows. For now, all such registers appear in the output as $0. Patch by Wouter van Oortmerssen Differential Revision: https://reviews.llvm.org/D45848 llvm-svn: 332052
* [mips] Correct the predicates of cvt.fmt.fmt instructionsSimon Dardis2018-05-102-0/+4
| | | | | | | | Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46390 llvm-svn: 331969
* [mips] Move conditional moves out of isCodeGenOnlySimon Dardis2018-05-092-0/+16
| | | | | | | | Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46389 llvm-svn: 331863
* [x86] Introduce the enclv instructionGabor Buella2018-05-082-0/+18
| | | | | | | | | | | | | | Summary: and use the -msgx flag as a requirement for the SGX instructions. Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D46436 llvm-svn: 331742
* [x86] Introduce the pconfig instructionGabor Buella2018-05-082-0/+6
| | | | | | | | | | Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D46430 llvm-svn: 331739
* [X86] movdiri and movdir64b instructionsGabor Buella2018-05-013-0/+27
| | | | | | | | | | Reviewers: spatel, craig.topper, RKSimon Reviewed By: craig.topper, RKSimon Differential Revision: https://reviews.llvm.org/D45983 llvm-svn: 331248
* [X86] Remove 'opaque ptr' from the intel syntax parser and printer.Craig Topper2018-05-012-7/+7
| | | | | | | | Previously for instructions like fxsave we would print "opaque ptr" as part of the memory operand. Now we print nothing. We also no longer accept "opaque ptr" in the parser. We still accept any size to be specified for these instructions, but we may want to consider only parsing when no explicit size is specified. This what gas does. llvm-svn: 331243
* AMDGPU: Add Vega12 and Vega20Matt Arsenault2018-04-301-0/+6
| | | | | | | | Changes by Matt Arsenault Konstantin Zhuravlyov llvm-svn: 331215
* [X86] Add suffixes to the LGDT/LIDT/SGDT/SIDT mnemonics in Intel syntax. Add ↵Craig Topper2018-04-291-4/+4
| | | | | | | | | | aliases based on 16/32-bit mode to choose the default. This allows the instruction selection to follow mode in Intel syntax. And allows a suffix to be used to change size. This matches gas behavior from what I could tell. llvm-svn: 331138
* [mips] Add support for Virtualization ASEPetar Jovanovic2018-04-276-0/+90
| | | | | | | | | | | | | | | | | | | This includes Instructions: tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr, hypcall mfgc0, mtgc0, mfhgc0, mthgc0, dmfgc0, dmtgc0, Assembler directives: .set virt, .set novirt, .module virt, .module novirt Attribute: virt .MIPS.abiflags: VZ (0x100) Patch by Vladimir Stefanovic. Differential Revision: https://reviews.llvm.org/D44905 llvm-svn: 331024
* [mips] Fix the definition of sync, synciSimon Dardis2018-04-251-0/+2
| | | | | | | | | | Also, fix the disassembly of synci for microMIPS. Reviewers: abeserminji, smaksimovic, atanasyan Differential Revision: https://reviews.llvm.org/D45870 llvm-svn: 330810
* [X86] Add a BSWAP16 instruction using the 32-bit encoding plus a 0x66 prefix.Craig Topper2018-04-241-1/+1
| | | | | | This encoding is recognized by the CPU, but the behavior is undefined. This makes the disassembler handle it correctly so we don't print bswapl with a 16-bit register. llvm-svn: 330682
* [X86] Revert r330638 - accidental commitGabor Buella2018-04-233-27/+0
| | | | llvm-svn: 330640
* [X86] movdiri and movdir64b instructionsGabor Buella2018-04-233-0/+27
| | | | | Reviewers: craig.topper llvm-svn: 330638
* [X86] Add disassembler test cases for bswap.Craig Topper2018-04-231-0/+9
| | | | | | | | This demonstrates a bug where the encoding for a 16-bit bswap prints a 16-bit register and a 32-bit mnemonic. Intel docs say 16-bit bswap is undefined. We should either claim it as an invalid encoding or we should print a 16-bit mnemonic. objdump does print the encoding as bswap with a 16-bit register. But it doesn't seem to ever print a suffix. llvm-svn: 330621
* [X86] Add VEX_WIG to VEX encoded version of VCMPPSY/VCMPPDY.Craig Topper2018-04-231-0/+6
| | | | llvm-svn: 330563
* [X86] WaitPKG instructionsGabor Buella2018-04-203-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Three new instructions: umonitor - Sets up a linear address range to be monitored by hardware and activates the monitor. The address range should be a writeback memory caching type. umwait - A hint that allows the processor to stop instruction execution and enter an implementation-dependent optimized state until occurrence of a class of events. tpause - Directs the processor to enter an implementation-dependent optimized state until the TSC reaches the value in EDX:EAX. Also modifying the description of the mfence instruction, as the rep prefix (0xF3) was allowed before, which would conflict with umonitor during disassembly. Before: $ echo 0xf3,0x0f,0xae,0xf0 | llvm-mc -disassemble .text mfence After: $ echo 0xf3,0x0f,0xae,0xf0 | llvm-mc -disassemble .text umonitor %rax Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45253 llvm-svn: 330462
* [AMDGPU][MC][VI][GFX9] Added support of SDWA/DPP for v_cndmask_b32Dmitry Preobrazhensky2018-04-163-1/+19
| | | | | | | | | See bug 36356: https://bugs.llvm.org/show_bug.cgi?id=36356 Differential Revision: https://reviews.llvm.org/D45446 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 330123
* [X86] Add the bizarro movsww and movzww mnemonics for the disassembler.Craig Topper2018-04-131-0/+18
| | | | | | | | The destination size of the movzx/movsx instruction is controlled by the normal operand size mechanisms. Only the input type is fixed. This means that a 0x66 prefix on the encoding for zext/sext 16->32 should really produce a 16->16 instruction. Functionally this is equivalent to a GR16->GR16 move since bits 16 and above will be preserved. So nothing is actually extended. llvm-svn: 330078
* [ARC] Add LImm support for J/JLYan Luo2018-04-131-0/+6
| | | | llvm-svn: 330031
* [X86] Introduce cldemote instructionGabor Buella2018-04-132-0/+12
| | | | | | | | | | | | | | Hint to hardware to move the cache line containing the address to a more distant level of the cache without writing back to memory. Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45256 llvm-svn: 329992
* [mips] Correct the predicates for special nops, tlb ctrl instrs, software ↵Simon Dardis2018-04-1218-0/+26
| | | | | | | | | | breakpoint and prefx. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905
* [X86] Describe wbnoinvd instructionGabor Buella2018-04-113-0/+9
| | | | | | | | | | | | | | | Similar to the wbinvd instruction, except this one does not invalidate caches. Ring 0 only. The encoding matches a wbinvd instruction with an F3 prefix. Reviewers: craig.topper, zvi, ashlykov Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D43816 llvm-svn: 329847
* [AMDGPU][MC][GFX9] Added v_screen_partition_4se_b32Dmitry Preobrazhensky2018-04-114-0/+16
| | | | | | | | | See bug 36845: https://bugs.llvm.org/show_bug.cgi?id=36845 Differential Revision: https://reviews.llvm.org/D45443 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 329801
* [AMDGPU][MC][GFX9] Added instructions s_mul_hi_*32, s_lshl*_add_u32Dmitry Preobrazhensky2018-04-091-0/+28
| | | | | | | | | | | See bugs 36841: https://bugs.llvm.org/show_bug.cgi?id=36841 36842: https://bugs.llvm.org/show_bug.cgi?id=36842 Differential Revision: https://reviews.llvm.org/D45251 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 329562
* [AMDGPU][MC][GFX9] Added s_call_b64Dmitry Preobrazhensky2018-04-061-0/+9
| | | | | | | | | See bug 36843: https://bugs.llvm.org/show_bug.cgi?id=36843 Differential Revision: https://reviews.llvm.org/D45268 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 329440
* [AMDGPU][MC][GFX9] Added instruction s_endpgm_ordered_ps_doneDmitry Preobrazhensky2018-04-061-0/+4
| | | | | | | | | See bug 36844: https://bugs.llvm.org/show_bug.cgi?id=36844 Differential Revision: https://reviews.llvm.org/D45313 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 329430
* [AMDGPU][MC][GFX9] Added instructions *saveexec*, *wrexec* and *bitreplicate*Dmitry Preobrazhensky2018-04-061-0/+34
| | | | | | | | | See bug 36840: https://bugs.llvm.org/show_bug.cgi?id=36840 Differential Revision: https://reviews.llvm.org/D45250 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 329419
* [AMDGPU][MC][VI][GFX9] Added s_atc_probe* instructionsDmitry Preobrazhensky2018-04-061-0/+12
| | | | | | | | | See bug 36839: https://bugs.llvm.org/show_bug.cgi?id=36839 Differential Revision: https://reviews.llvm.org/D45249 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 329408
* [ARC] Add <.f> suffix for F32_GEN4_{DOP|SOP}.Pete Couperus2018-04-061-0/+24
| | | | | | | | | Add disassembler support for instructions which writeback STATUS32. https://reviews.llvm.org/D45148 Patch by Yan Luo! (Yan.Luo2@synopsys.com) llvm-svn: 329404
* [AMDGPU][MC][GFX9] Added s_dcache_discard* instructionsDmitry Preobrazhensky2018-04-061-0/+16
| | | | | | | | | See bug 36838: https://bugs.llvm.org/show_bug.cgi?id=36838 Differential Revision: https://reviews.llvm.org/D45247 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 329397
* [AMDGPU][MC][GFX9] Added instructions v_cvt_norm_*16_f16, v_sat_pk_u8_i16Dmitry Preobrazhensky2018-04-023-0/+60
| | | | | | | | | See bug 36847: https://bugs.llvm.org/show_bug.cgi?id=36847 Differential Revision: https://reviews.llvm.org/D45097 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 328988
* [AMDGPU][MC][GFX9] Added s_atomic_* and s_buffer_atomic_* instructionsDmitry Preobrazhensky2018-04-021-0/+192
| | | | | | | | | | | Fixed a bug which caused Tablegen crash. See bug 36837: https://bugs.llvm.org/show_bug.cgi?id=36837 Differential Revision: https://reviews.llvm.org/D45085 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 328983
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