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* [AMDGPU] Add intrinsics for tbuffer load and storeDavid Stuttard2017-06-221-0/+22
| | | | | | | | | | | | | | | Intrinsic already existed for llvm.SI.tbuffer.store Needed tbuffer.load and also re-implementing the intrinsic as llvm.amdgcn.tbuffer.* Added CodeGen tests for the 2 new variants added. Left the original llvm.SI.tbuffer.store implementation to avoid issues with existing code Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, tpr Differential Revision: https://reviews.llvm.org/D30687 llvm-svn: 306031
* [AMDGPU][MC][GFX9] Corrected VOP3P relevant code to fix disassembler failuresDmitry Preobrazhensky2017-06-211-0/+1752
| | | | | | | | | | See Bug 33509: https://bugs.llvm.org//show_bug.cgi?id=33509 Reviewers: Sam Kolton, Artem Tamazov, Valery Pykhtin Differential Revision: https://reviews.llvm.org/D34360 llvm-svn: 305923
* [AMDGPU][mc][tests][NFC] Bulk ISA tests: Massive update. Add Gfx9 dasm tests.Artem Tamazov2017-06-192-22719/+125593
| | | | | | | | | | | A new Gfx9 dasm test added with approx 29000 cases. Existing tests extended by (approx.): * Gfx7 asm: 5000 test cases * Gfx8 asm: 5000 test cases * Gfx9 asm: 14400 test cases * Gfx8 dasm: 5200 test cases llvm-svn: 305702
* [Power9] Added support for the modsw, moduw, modsd, modud hardware instructions.Tony Jiang2017-06-122-0/+24
| | | | | | | | | | | Note that if we need the result of both the divide and the modulo then we compute the modulo based on the result of the divide and not using the new hardware instruction. Commit on behalf of STEFAN PINTILIE. Differential Revision: https://reviews.llvm.org/D33940 llvm-svn: 305210
* [mips][dsp] Modify repl.ph to accept signed immediate valuesPetar Jovanovic2017-06-071-1/+1
| | | | | | | | | | | | Changed immediate type for repl.ph from uimm10 to simm10 as per the specs. Repl.qb still accepts uimm8. Both instructions now mimic the behaviour of GNU as. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D33594 llvm-svn: 304918
* [AMDGPU][MC] New syntax for ds_swizzle_b32 offsetDmitry Preobrazhensky2017-05-311-10/+10
| | | | | | | | | | See Bug 28601: https://bugs.llvm.org//show_bug.cgi?id=28601 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D33542 llvm-svn: 304309
* [SystemZ] Add decimal floating-point instructionsUlrich Weigand2017-05-302-0/+1530
| | | | | | | | | This adds assembler / disassembler support for the decimal floating-point instructions. Since LLVM does not yet have support for decimal float types, these cannot be used for codegen at this point. llvm-svn: 304203
* [SystemZ] Add hexadecimal floating-point instructionsUlrich Weigand2017-05-301-1/+1689
| | | | | | | | This adds assembler / disassembler support for the hexadecimal floating-point instructions. Since the Linux ABI does not use any hex float data types, these are not useful for codegen. llvm-svn: 304202
* [SystemZ] Add missing assembler/disassembler testsUlrich Weigand2017-05-301-0/+66
| | | | | | | A few instructions that are actually correctly supported in the assembler and disassembler did not have any tests. llvm-svn: 304200
* [AMDGPU] SDWA: add disassembler support for GFX9Sam Kolton2017-05-261-0/+477
| | | | | | | | | | | | Summary: Added decoder methods and tests Reviewers: vpykhtin, artem.tamazov, dp Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D33545 llvm-svn: 303999
* [X86] Adding vpopcntd and vpopcntq instructionsOren Ben Simhon2017-05-251-0/+23
| | | | | | | | | AVX512_VPOPCNTDQ is a new feature set that was published by Intel. The patch represents the LLVM side of the addition of two new intrinsic based instructions (vpopcntd and vpopcntq). Differential Revision: https://reviews.llvm.org/D33169 llvm-svn: 303858
* [AMDGPU][MC] Corrected disassembler to decode instructions with 2 literalsDmitry Preobrazhensky2017-05-191-0/+3
| | | | | | | | | | See bug 32922: https://bugs.llvm.org//show_bug.cgi?id=32922 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D32912 llvm-svn: 303428
* [AMDGPU][MC] Fixed bugs in export instructionDmitry Preobrazhensky2017-05-191-0/+40
| | | | | | | | | | | | See Bugs 33019, 33056: https://bugs.llvm.org//show_bug.cgi?id=33019 https://bugs.llvm.org//show_bug.cgi?id=33056 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D33288 llvm-svn: 303423
* [AMDGPU][MC] Corrected several VI opcodes to avoid printing _e64Dmitry Preobrazhensky2017-05-151-11/+11
| | | | | | | | | | See bug 32936: https://bugs.llvm.org//show_bug.cgi?id=32936 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D33123 llvm-svn: 303070
* [AMDGPU][MC] Removed V_MQSAD_U16_U8Dmitry Preobrazhensky2017-05-151-0/+18
| | | | | | | | | | | | This instruction does not really exist See Bug 33018: https://bugs.llvm.org//show_bug.cgi?id=33018 Reviewers: vpykhtin, artem.tamazov Differential Revision: https://reviews.llvm.org/D33126 llvm-svn: 303055
* [PPC] Change the register constraint of the first source operand of ↵Guozhi Wei2017-05-111-0/+4
| | | | | | | | | | | | instruction mtvsrdd to g8rc_nox0 According to Power ISA V3.0 document, the first source operand of mtvsrdd is constant 0 if r0 is specified. So the corresponding register constraint should be g8rc_nox0. This bug caused wrong output generated by 401.bzip2 when -mcpu=power9 and fdo are specified. Differential Revision: https://reviews.llvm.org/D32880 llvm-svn: 302834
* AMDGPU: Remove tfe bit from flat instruction definitionsMatt Arsenault2017-05-111-24/+0
| | | | | | | | | | We don't use it and it was removed in gfx9, and the encoding bit repurposed. Additionally actually using it requires changing the output register class, which wasn't done anyway. llvm-svn: 302814
* [SystemZ] Add miscellaneous instructionsUlrich Weigand2017-05-101-0/+117
| | | | | | | | This adds a few missing instructions for the assembler and disassembler. Those should be the last missing general- purpose (Chapter 7) instructions for the z10 ISA. llvm-svn: 302667
* [SystemZ] Add missing arithmetic instructionsUlrich Weigand2017-05-101-0/+645
| | | | | | | | | This adds the remaining general arithmetic instructions for assembler / disassembler use. Most of these are not useful for codegen; a few might be, and those are listed in the README.txt for future improvements. llvm-svn: 302665
* [AMDGPU][MC] Corrected v_madak/madmk to avoid printing "_e32" in ↵Dmitry Preobrazhensky2017-05-102-7/+7
| | | | | | | | | | | | disassembler output See bug 32927: https://bugs.llvm.org//show_bug.cgi?id=32927 Reviewers: vpykhtin, artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D32913 llvm-svn: 302648
* [SystemZ] Add decimal integer instructionsUlrich Weigand2017-05-101-0/+888
| | | | | | | This adds the set of decimal integer (BCD) instructions for assembler / disassembler use. llvm-svn: 302646
* [SystemZ] Add crypto instructionsUlrich Weigand2017-05-102-0/+111
| | | | | | | This adds the set of message-security assist instructions for assembler / disassembler use. llvm-svn: 302645
* [SystemZ] Add translate/convert instructionsUlrich Weigand2017-05-101-0/+324
| | | | | | | This adds the set of character-set translate and convert instructions for assembler / disassembler use. llvm-svn: 302644
* [SystemZ] Add missing memory/string instructionsUlrich Weigand2017-05-101-0/+186
| | | | | | | This adds a number of missing memory and string instructions for assembler / disassembler use. llvm-svn: 302643
* [SystemZ] Reformat assembler/disassembler testsUlrich Weigand2017-05-102-4198/+4228
| | | | | | | | The assembler and disassmebler test cases started out formatted and sorted in a particular way, but this got lost over time as patches were added. Reformat them again. NFC. llvm-svn: 302642
* [AArch64] armv8-A doesn't have CRC.Ahmed Bougacha2017-05-031-17/+0
| | | | | | | | | | | That's only a required extension as of v8.1a. Remove it from the "generic" CPU as well: it should only support the base ISA (and binutils agrees). Also unify the MC tests into crc.s and arm64-crc32.s llvm-svn: 302077
* [X86][LWP] Add llvm support for LWP instructions (reapplied).Simon Pilgrim2017-05-032-0/+42
| | | | | | | | | | This patch adds support for the the LightWeight Profiling (LWP) instructions which are available on all AMD Bulldozer class CPUs (bdver1 to bdver4). Reapplied - this time without changing line endings of existing files. Differential Revision: https://reviews.llvm.org/D32769 llvm-svn: 302041
* Revert rL302028 due to accidental line ending changes.Simon Pilgrim2017-05-032-42/+0
| | | | llvm-svn: 302038
* [X86][LWP] Add llvm support for LWP instructions.Simon Pilgrim2017-05-032-0/+42
| | | | | | | | This patch adds support for the the LightWeight Profiling (LWP) instructions which are available on all AMD Bulldozer class CPUs (bdver1 to bdver4). Differential Revision: https://reviews.llvm.org/D32769 llvm-svn: 302028
* [X86][SSE2] Fix asm string for movq (Move Quadword) instruction.Ayman Musa2017-04-261-4/+4
| | | | | | | | Replace "mov{d|q}" with "movq". Differential Revision: https://reviews.llvm.org/D32220 llvm-svn: 301386
* [AMDGPU][mc][tests][NFC] Bulk ISA tests: update for Gfx7/Gfx8, add for Gfx9.Artem Tamazov2017-04-241-57799/+65599
| | | | llvm-svn: 301247
* [AMDGPU][MC] Corrected src0 size for s_cbranch_joinDmitry Preobrazhensky2017-04-121-1/+1
| | | | | | | | | | Fix for bug 28159: https://bugs.llvm.org//show_bug.cgi?id=28159 Reviewers: vpykhtin, arsenm Differential Revision: https://reviews.llvm.org/D31595 llvm-svn: 300055
* AMDGPU: Fix crash when disassembling VOP3 macMatt Arsenault2017-04-101-0/+19
| | | | | | | | | | | | The unused dummy src2_modifiers is missing, so it crashes when trying to print it. I tried to fully remove src2_modifiers, but there are some irritations in the places where it is converted to mad since it starts to require modifying use lists while iterating over them. llvm-svn: 299861
* [AMDGPU][MC] Fix for Bug 28211 + LIT testsDmitry Preobrazhensky2017-04-071-10/+16
| | | | | | | | | | | | | | | | | | | | - corrected DS_GWS_* opcodes (see VI_Shader_Programming#16.pdf for detailed description) - address operand is not used - several opcodes have data operand - all opcodes have offset modifier - DS_AND_SRC2_B32: corrected typo in mnemo - DS_WRAP_RTN_F32 replaced with DS_WRAP_RTN_B32 - added CI/VI opcodes: - DS_CONDXCHG32_RTN_B64 - DS_GWS_SEMA_RELEASE_ALL - added VI opcodes: - DS_CONSUME - DS_APPEND - DS_ORDERED_COUNT Differential Revision: https://reviews.llvm.org/D31707 llvm-svn: 299767
* [AMDGPU][MC] Fix for Bugs 28200, 28202 + LIT testsDmitry Preobrazhensky2017-03-201-0/+6
| | | | | | | | | | Fixed several related issues with VOP3 fp modifiers. Reviewers: artem.tamazov Differential Revision: https://reviews.llvm.org/D30821 llvm-svn: 298255
* [PowerPC][Altivec] Add mfvrd and mffprd extended mnemonicNemanja Ivanovic2017-03-151-2/+2
| | | | | | | | | | | mfvrd and mffprd are both alias to mfvrsd. This patch enables correct parsing of the aliases, but we still emit a mfvrsd. Committing on behalf of brunoalr (Bruno Rosa). Differential Revision: https://reviews.llvm.org/D29177 llvm-svn: 297849
* AMDGPU: Add definition for v_swap_b32Matt Arsenault2017-02-281-0/+4
| | | | | | | | This is somewhat tricky because there are two pairs of tied operands, and it isn't allowed to be VOP3 encoded. llvm-svn: 296519
* AMDGPU: Fix disassembly of aperture registersMatt Arsenault2017-02-181-0/+13
| | | | llvm-svn: 295555
* AMDGPU: Replace assert with report_fatal_errorMatt Arsenault2017-02-151-0/+4
| | | | | | Also use a more refined condition. llvm-svn: 295239
* [Hexagon] Replace instruction definitions with auto-generated onesKrzysztof Parzyszek2017-02-1018-931/+931
| | | | llvm-svn: 294753
* [X86] Clzero intrinsic and its addition under znver1Craig Topper2017-02-091-0/+3
| | | | | | | | | | | | | | | | | This patch does the following. 1. Adds an Intrinsic int_x86_clzero which works with __builtin_ia32_clzero 2. Identifies clzero feature using cpuid info. (Function:8000_0008, Checks if EBX[0]=1) 3. Adds the clzero feature under znver1 architecture. 4. The custom inserter is added in Lowering. 5. A testcase is added to check the intrinsic. 6. The clzero instruction is added to assembler test. Patch by Ganesh Gopalasubramanian with a couple formatting tweaks, a disassembler test, and using update_llc_test.py from me. Differential revision: https://reviews.llvm.org/D29385 llvm-svn: 294558
* Revert r294437 as it broke an asan buildbot.Amara Emerson2017-02-081-24/+24
| | | | llvm-svn: 294523
* [AArch64][TableGen] Skip tied result operands for InstAliasAmara Emerson2017-02-081-24/+24
| | | | | | | | | | | | | | | | | | | | | | | This patch checks the number of operands in the resulting instruction instead of just the alias, then skips over tied operands when generating the printing method. This allows us to generate the preferred assembly syntax for the AArch64 'ins' instruction, which should always be displayed as 'mov' according to the ARMARM. Several unit tests have changed as a result, but only to reflect the preferred disassembly. Some other InstAlias patterns (movk/bic/orr) needed a slight adjustment to stop them becoming the default and breaking other unit tests. Patch by Graham Hunter. Differential Revision: https://reviews.llvm.org/D29219 llvm-svn: 294437
* [X86] Remove PCOMMIT instruction support since Intel has deprecated this ↵Craig Topper2017-02-081-3/+0
| | | | | | | | instruction with no plans to release products with it. Intel's documentation for the deprecation https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction llvm-svn: 294405
* [Hexagon] Adding gp+ to the syntax of gp-relative instructionsKrzysztof Parzyszek2017-02-063-14/+14
| | | | | | Patch by Colin LeMahieu. llvm-svn: 294258
* [X86] Fix printing of sha256rnds2 to include the implicit %xmm0 argument.Craig Topper2017-02-051-2/+2
| | | | llvm-svn: 294132
* Reapply [AMDGPU][mc][tests][NFC] Add coverage/smoke tests for Gfx7 and Gfx8.Artem Tamazov2017-01-301-0/+87676
| | | | llvm-svn: 293552
* [X86][Disassembler] Added SALC instructionChris Ray2017-01-291-790/+793
| | | | | | | | | | | | Reviewers: joe.abbey, craig.topper Reviewed By: craig.topper Subscribers: majnemer, llvm-commits Differential Revision: https://reviews.llvm.org/D29201 llvm-svn: 293447
* Add some Book-E instructions to the asm parser and printer.Justin Hibbits2017-01-291-0/+9
| | | | | | | | | | | | | | | | | | | Summary: Adds the following instructions: * mfpmr * mtpmr * icblc * icblq * icbtls Fix the scheduling for mtspr on e5500, which uses CFX0, instead of SFX0/SFX1 as on e500mc. Addresses PR 31538. Differential Revision: https://reviews.llvm.org/D29002 llvm-svn: 293417
* [X86] Adding FFREEP instruction.Chris Ray2017-01-271-1037/+1061
| | | | | | | | | | | | | | Summary: Small change to get the FREEP instruction to decode properly. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29193 llvm-svn: 293314
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