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* [AMDGPU][MC] Added support of 64-bit image atomicsDmitry Preobrazhensky2018-01-261-0/+32
| | | | | | | | | See bug 35998: https://bugs.llvm.org/show_bug.cgi?id=35998 Differential Revision: https://reviews.llvm.org/D42469 Reviewers: vpykhtin, artem.tamazov, arsenm llvm-svn: 323534
* [AMDGPU][MC] Enabled disassembler for image atomic operationsDmitry Preobrazhensky2018-01-261-0/+32
| | | | | | | | | See bug 35988: https://bugs.llvm.org/show_bug.cgi?id=35988 Differential Revision: https://reviews.llvm.org/D42186 Reviewers: vpykhtin, artem.tamazov, arsenm llvm-svn: 323527
* [mips] Properly select abs and sqrt instructionsStefan Maksimovic2018-01-2312-0/+78
| | | | | | | | | | | | | - Alter abs for micromips to have both AFGR64 and FGR64 variants, same as sqrt - Remove sqrt and abs from MicroMips32r6InstrInfo.td, use micromips FGR64 variants - Restrict non-micromips abs/sqrt with NotInMicroMips predicate Differential revision: https://reviews.llvm.org/D41439 llvm-svn: 323184
* [AMDGPU][MC][GFX9] Enable inline constants for SDWA operandsDmitry Preobrazhensky2018-01-171-0/+100
| | | | | | | | | See bug 35771: https://bugs.llvm.org/show_bug.cgi?id=35771 Differential Revision: https://reviews.llvm.org/D42058 Reviewers: vpykhtin, artem.tamazov, arsenm llvm-svn: 322655
* [X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics.Craig Topper2018-01-121-2/+2
| | | | | | While the suffix isn't required to disambiguate the instructions, it is required in order to parse the instructions when the suffix is specified in order to match the GNU assembler. llvm-svn: 322354
* [AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK supportDmitry Preobrazhensky2018-01-102-1/+16
| | | | | | | | | See bug 35764: https://bugs.llvm.org/show_bug.cgi?id=35764 Differential Revision: https://reviews.llvm.org/D41614 Reviewers: vpykhtin, artem.tamazov, arsenm llvm-svn: 322189
* [X86] Stop printing moves between VR64 and GR64 with 'movd' mnemonic. Use ↵Craig Topper2018-01-051-4/+4
| | | | | | | | 'movq' instead. This behavior existed to work with an old version of the gnu assembler on MacOS that only accepted this form. Newer versions of GNU assembler and the current LLVM derived version of the assembler on MacOS support movq as well. llvm-svn: 321898
* [AMDGPU][MC] Incorrect parsing of flat/global atomic modifiersDmitry Preobrazhensky2017-12-291-0/+12
| | | | | | | | | See bug 35730: https://bugs.llvm.org/show_bug.cgi?id=35730 Differential Revision: https://reviews.llvm.org/D41598 Reviewers: vpykhtin, artem.tamazov, arsenm llvm-svn: 321552
* [AMDGPU][MC] Corrected parsing of optional operands for ds_swizzle_b32Dmitry Preobrazhensky2017-12-221-0/+3
| | | | | | | | | | See bug 35645: https://bugs.llvm.org/show_bug.cgi?id=35645 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D41186 llvm-svn: 321367
* [AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registersDmitry Preobrazhensky2017-12-222-0/+48
| | | | | | | | | | | | See bug 35561: https://bugs.llvm.org/show_bug.cgi?id=35561 This patch also affects implementation of SGPR and VGPR registers though changes are cosmetic. Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D41437 llvm-svn: 321359
* [X86] Add prefetchwt1 instruction and overhaul priorities and isel enabling ↵Craig Topper2017-12-221-0/+3
| | | | | | | | | | | | | | for prefetch instructions. Previously prefetch was only considered legal if sse was enabled, but it should be supported with 3dnow as well. The prfchw flag now imply at least some form of prefetch without the write hint is available, either the sse or 3dnow version. This is true even if 3dnow and sse are explicitly disabled. Similarly prefetchwt1 feature implies availability of prefetchw and the the prefetcht0/1/2/nta instructions. This way we can support _MM_HINT_ET0 using prefetchw and _MM_HINT_ET1 with prefetchwt1. And its assumed that if we have levels for the write hint we would have levels for the non-write hint, thus why we enable the sse prefetch instructions. I believe this behavior is consistent with gcc. I've updated the prefetch.ll to test all of these combinations. llvm-svn: 321335
* [ARM] Armv8-R DFB instructionSam Parker2017-12-212-0/+12
| | | | | | | | Implement MC support for the Armv8-R 'Data Full Barrier' instruction. Differential Revision: https://reviews.llvm.org/D41430 llvm-svn: 321256
* [AArch64] CCSIDR2 system registerSam Parker2017-12-201-0/+3
| | | | | | | | | | Implement the 'Current Cache Size' register that has been introduced as part of the Armv8.3 architecture. I originally missed this, and (hopefully) should be the final patch for assembler support. Differential Revision: https://reviews.llvm.org/D41396 llvm-svn: 321155
* AMDGPU: Partially fix disassembly of MIMG instructionsMatt Arsenault2017-12-131-0/+39
| | | | | | | | | | | | | | | | | | | | | Stores failed to decode at all since they didn't have a DecoderNamespace set. Loads worked, but did not change the register width displayed to match the numbmer of enabled channels. The number of printed registers for vaddr is still wrong, but I don't think that's encoded in the instruction so there's not much we can do about that. Image atomics are still broken. MIMG is the same encoding for SI/VI, but the image atomic classes are split up into encoding specific versions unlike every other MIMG instruction. They have isAsmParserOnly set on them for some reason. dmask is also special for these, so we probably should not have it as an explicit operand as it is now. llvm-svn: 320614
* [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tmaDmitry Preobrazhensky2017-12-112-0/+118
| | | | | | | | | | | | See bugs 35494 and 35559: https://bugs.llvm.org/show_bug.cgi?id=35494 https://bugs.llvm.org/show_bug.cgi?id=35559 Reviewers: vpykhtin, artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D41007 llvm-svn: 320375
* [mips] Removal of microMIPS64R6Aleksandar Beserminji2017-12-111-324/+0
| | | | | | | | | | | All files and parts of files related to microMIPS4R6 are removed. When target is microMIPS4R6, errors are printed. This is LLVM part of patch. Differential Revision: https://reviews.llvm.org/D35625 llvm-svn: 320350
* PowerPC: support external pid instructions in MC layer.Tim Northover2017-12-101-0/+34
| | | | | | | | | | | This adds assembly & disassembly support for the e500mc "external pid" instructions. See https://reviews.llvm.org/D39249. Patch by vit9696 <vit9696@avp.su> llvm-svn: 320287
* AMDGPU/GCN: Bring processors in sync with AMDGPUUsageKonstantin Zhuravlyov2017-12-084-4/+4
| | | | | | | | | | | | - Add gfx704 - Change bonaire to gfx704 - Remove gfx804 - Remove gfx901 - Remove gfx903 Differential Revision: https://reviews.llvm.org/D40046 llvm-svn: 320194
* [ARC] Add instruction subset for the ARC backend.Tatyana Krasnukha2017-12-023-0/+394
| | | | | | | | | | | | Reviewers: petecoup, kparzysz Reviewed By: petecoup Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37983 llvm-svn: 319609
* [AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodesDmitry Preobrazhensky2017-11-271-0/+85
| | | | | | | | | See bug 35433: https://bugs.llvm.org/show_bug.cgi?id=35433 Differential Revision: https://reviews.llvm.org/D40493 Reviewers: artem.tamazov, SamWot, arsenm llvm-svn: 319050
* [AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16Dmitry Preobrazhensky2017-11-241-0/+36
| | | | | | | | | | See bug 33629: https://bugs.llvm.org//show_bug.cgi?id=33629 Reviewers: artem.tamazov, SamWot, arsenm Differential Revision: https://reviews.llvm.org/D39488 llvm-svn: 318955
* [Hexagon] Remove trailing spaces, NFCKrzysztof Parzyszek2017-11-221-2/+2
| | | | llvm-svn: 318875
* [AMDGPU][mc][tests] Updated generated lit tests for GFX8/9Dmitry Preobrazhensky2017-11-222-0/+4602
| | | | | | | | Summary: Added tests to better cover features introduced by commit rL318675. See http://llvm.org/viewvc/llvm-project?view=revision&revision=318675 llvm-svn: 318841
* Avoid unecessary opsize byte in segment move to memoryNirav Dave2017-11-211-2/+2
| | | | | | | | | | | | | | | | | Segment moves to memory are always 16-bit. Remove invalid 32 and 64 bit variants. Recommiting with missing clang inline assembly test change. Fixes PR34478. Reviewers: rnk, craig.topper Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D39847 llvm-svn: 318797
* [AMDGPU] SDWA: remove omod src operand for VOP2b instructionsSam Kolton2017-11-212-0/+35
| | | | | | | | | | | | Summary: VOP2b instructions (v_subbrev_u32, v_add_i32 ...) shouldn't support OMod operand in SDWA encoding Reviewers: rampitec, dp Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D40172 llvm-svn: 318761
* Revert r318678 to fix Clang testRichard Trieu2017-11-211-2/+2
| | | | | | r318678 caused the Clang test CodeGen/ms-inline-asm.c to start failing. llvm-svn: 318710
* [X86] Avoid unecessary opsize byte in segment move to memoryNirav Dave2017-11-201-2/+2
| | | | | | | | | | | | | | | | | Summary: Segment moves to memory are always 16-bit. Remove invalid 32 and 64 bit variants. Fixes PR34478. Reviewers: rnk, craig.topper Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D39847 llvm-svn: 318678
* [AMDGPU][MC][GFX8][GFX9] Corrected names of integer ↵Dmitry Preobrazhensky2017-11-201-14/+14
| | | | | | | | | | | | v_{add/addc/sub/subrev/subb/subbrev} See bug 34765: https://bugs.llvm.org//show_bug.cgi?id=34765 Reviewers: tamazov, SamWot, arsenm, vpykhtin Differential Revision: https://reviews.llvm.org/D40088 llvm-svn: 318675
* [AArch64][TableGen] Skip tied result operands for InstAliasSander de Smalen2017-11-201-24/+24
| | | | | | | | | | | | | | | | | | | | Summary: This patch fixes an issue so that the right alias is printed when the instruction has tied operands. It checks the number of operands in the resulting instruction as opposed to the alias, and then skips over tied operands that should not be printed in the alias. This allows to generate the preferred assembly syntax for the AArch64 'ins' instruction, which should always be displayed as 'mov' according to the ARM Architecture Reference Manual. Several unit tests have changed as a result, but only to reflect the preferred disassembly. Some other InstAlias patterns (movk/bic/orr) needed a slight adjustment to stop them becoming the default and breaking other unit tests. Please note that the patch is mostly the same as https://reviews.llvm.org/D29219 which was reverted because of an issue found when running TableGen with the Address Sanitizer. That issue has been addressed in this iteration of the patch. Reviewers: rengolin, stoklund, huntergr, SjoerdMeijer, rovka Reviewed By: rengolin, SjoerdMeijer Subscribers: fhahn, aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D40030 llvm-svn: 318650
* [MC][X86] Add test case from PR19251Simon Pilgrim2017-11-181-0/+4
| | | | llvm-svn: 318605
* [MC][X86] Add teet case from PR32807Simon Pilgrim2017-11-181-0/+3
| | | | llvm-svn: 318603
* [AMDGPU][MC][GFX9][disassembler] Corrected decoding of op_sel_hi for v_mad_mix*Dmitry Preobrazhensky2017-11-171-0/+441
| | | | | | | | | | See bug 35148: https://bugs.llvm.org//show_bug.cgi?id=35148 Reviewers: tamazov, SamWot, arsenm Differential Revision: https://reviews.llvm.org/D39492 llvm-svn: 318526
* Reland "[mips][mt][6/7] Add support for mftr, mttr instructions."Simon Dardis2017-11-142-2/+40
| | | | | | | | | | | | | | | | | | | | This adjusts the tests to hopfully pacify the llvm-clang-x86_64-expensive-checks-win buildbot. Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 318207
* [mips] Add movep for microMIPS32R6 and fix microMIPS32r3 versionSimon Dardis2017-11-064-2/+4
| | | | | | | | | | | | | | | | | | | Previously, the 'movep' instruction was defined for microMIPS32r3 and shared that definition with microMIPS32R6. 'movep' was re-encoded for microMIPS32r6, so this patch provides the correct encoding. Secondly, correct the encoding of the 'rs' and 'rt' operands which have an instruction specific encoding for the registers those operands accept. Finally, correct the decoding of the 'dst_regs' operand which was extracting the relevant field from the instruction, but was actually extracting the field from the alreadly extracted field. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39495 llvm-svn: 317475
* Fix for Bug 34475 - LOCK/REP/REPNE prefixes emitted as instruction on their own.Andrew V. Tischenko2017-11-034-118/+59
| | | | | | Differential Revision: https://reviews.llvm.org/D39546 llvm-svn: 317330
* Invalid used of 'w' suffix on push and pop using 64-bit register.Andrew V. Tischenko2017-10-301-4/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D38626 llvm-svn: 316898
* [mips] Fix (dis)assembly of abs.fmt for micromipsSimon Dardis2017-10-262-0/+4
| | | | | | | | | | | These instructions were previously marked as codegen only preventing them from being assembled as microMIPS or disassembled. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D39123 llvm-svn: 316656
* It's a test to demonstrate wrong disassembler with 0x67 prefixAndrew V. Tischenko2017-10-261-0/+8
| | | | llvm-svn: 316655
* [X86] Add PTWRITE instruction for assembler and disassembler.Craig Topper2017-10-232-0/+17
| | | | llvm-svn: 316333
* [X86] Add RDPID instruction for assembler and disassembler.Craig Topper2017-10-232-0/+6
| | | | llvm-svn: 316332
* Fix for Bug 30718 - Failure to disassemble certain MOV with rex.R. The issue ↵Andrew V. Tischenko2017-10-231-0/+3
| | | | | | | | was in illegal segment register index. Differential Revision: https://reviews.llvm.org/D38786 llvm-svn: 316319
* [X86] Fix disassembly of EVEX rounding control and SAE instructions.Craig Topper2017-10-231-0/+80
| | | | | | Fixes PR31955. llvm-svn: 316308
* [X86] Teach the disassembler that some instructions use VEX.W==0 without a ↵Craig Topper2017-10-221-0/+11
| | | | | | | | corresponding VEX.W==1 instruction and we shouldn't treat them as if VEX.W is ignored. Fixes PR11304. llvm-svn: 316285
* [X86] Don't allow gather/scatter to disassembler if memory operand does not ↵Craig Topper2017-10-221-0/+4
| | | | | | | | use a SIB byte. Fixes PR34998. llvm-svn: 316282
* [X86] Fix disassembling of EVEX instructions to stop accidentally decoding ↵Craig Topper2017-10-211-12/+4
| | | | | | | | | | | | the SIB index register as an XMM/YMM/ZMM register. This introduces a new operand type to encode the whether the index register should be XMM/YMM/ZMM. And new code to fixup the results created by readSIB. This has the nice effect of removing a bunch of code that hard coded the name of every GATHER and SCATTER instruction to map the index type. This fixes PR32807. llvm-svn: 316273
* [ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM modeAndre Vieira2017-10-182-0/+85
| | | | | | Differential Revision: https://reviews.llvm.org/D38347 llvm-svn: 316085
* More tests with x86 prefixes which work after rL315899 commitAndrew V. Tischenko2017-10-172-0/+125
| | | | llvm-svn: 315983
* [mips][micromips] Fix (dis)assembly of bc1(t|f)Simon Dardis2017-10-162-0/+4
| | | | | | | | | | | | Previously these instructions were marked codegen only and had an under-specified instruction description that did not record the fcc register. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D38847 llvm-svn: 315905
* This patch is a result of D37262: The issues with X86 prefixes. It closes ↵Andrew V. Tischenko2017-10-163-1/+81
| | | | | | PR7709, PR17697, PR19251, PR32809 and PR21640. There could be other bugs closed by this patch. llvm-svn: 315899
* [mips] Place certain 64 bit FPU instructions in their own decoder namespaceSimon Dardis2017-10-056-0/+6
| | | | | | | | | | | Previously, instructions that were defined to use the FGR64 register class were associated with the Mips64 table which was incorrect. Reviewers: nitesh.jain, atanasyan Differential Revision: https://reviews.llvm.org/D38454 llvm-svn: 314976
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