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* It's a test to demonstrate wrong disassembler with 0x67 prefixAndrew V. Tischenko2017-10-261-0/+8
| | | | llvm-svn: 316655
* [X86] Add PTWRITE instruction for assembler and disassembler.Craig Topper2017-10-232-0/+17
| | | | llvm-svn: 316333
* [X86] Add RDPID instruction for assembler and disassembler.Craig Topper2017-10-232-0/+6
| | | | llvm-svn: 316332
* Fix for Bug 30718 - Failure to disassemble certain MOV with rex.R. The issue ↵Andrew V. Tischenko2017-10-231-0/+3
| | | | | | | | was in illegal segment register index. Differential Revision: https://reviews.llvm.org/D38786 llvm-svn: 316319
* [X86] Fix disassembly of EVEX rounding control and SAE instructions.Craig Topper2017-10-231-0/+80
| | | | | | Fixes PR31955. llvm-svn: 316308
* [X86] Teach the disassembler that some instructions use VEX.W==0 without a ↵Craig Topper2017-10-221-0/+11
| | | | | | | | corresponding VEX.W==1 instruction and we shouldn't treat them as if VEX.W is ignored. Fixes PR11304. llvm-svn: 316285
* [X86] Don't allow gather/scatter to disassembler if memory operand does not ↵Craig Topper2017-10-221-0/+4
| | | | | | | | use a SIB byte. Fixes PR34998. llvm-svn: 316282
* [X86] Fix disassembling of EVEX instructions to stop accidentally decoding ↵Craig Topper2017-10-211-12/+4
| | | | | | | | | | | | the SIB index register as an XMM/YMM/ZMM register. This introduces a new operand type to encode the whether the index register should be XMM/YMM/ZMM. And new code to fixup the results created by readSIB. This has the nice effect of removing a bunch of code that hard coded the name of every GATHER and SCATTER instruction to map the index type. This fixes PR32807. llvm-svn: 316273
* More tests with x86 prefixes which work after rL315899 commitAndrew V. Tischenko2017-10-172-0/+125
| | | | llvm-svn: 315983
* This patch is a result of D37262: The issues with X86 prefixes. It closes ↵Andrew V. Tischenko2017-10-163-1/+81
| | | | | | PR7709, PR17697, PR19251, PR32809 and PR21640. There could be other bugs closed by this patch. llvm-svn: 315899
* [X86] Run dos2unix on two disassembler tests.Craig Topper2017-10-022-1854/+1854
| | | | llvm-svn: 314727
* [X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMemCraig Topper2017-10-011-2/+2
| | | | | | | | | | | | | | | | | | | Summary: Intel documentation shows the memory operand as the first operand. But we currently treat it as the second operand. Conceptually the order doesn't matter since it doesn't write memory. We have aliases to parse with the operands in either order and the isel matching is commutable. For the register&register form order does matter for the assembly parser. PR22995 was previously filed and fixed by changing the register&register form from MRMSrcReg to MRMDestReg to match gas. Ideally the memory form should match by using MRMDestMem. I believe this supercedes D38025 which was trying to switch the register&register form back to pre-PR22995. Reviewers: aymanmus, RKSimon, zvi Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38120 llvm-svn: 314639
* 'into' instruction should not be decoded as a valid instr in 64-bit modeAndrew V. Tischenko2017-09-201-0/+6
| | | | llvm-svn: 313735
* Revert "The current version of LLVM X86 disassembler incorrectly interprets ↵Eric Christopher2017-08-293-133/+1
| | | | | | | | some possible sets of x86 prefixes. This patch is the first step to close PR7709 and PR17697. There will be next patch(es) to close relative PRs." temporarily while some regressions are addressed. This reverts commit r311882. llvm-svn: 311987
* The current version of LLVM X86 disassembler incorrectly interprets some ↵Andrew V. Tischenko2017-08-283-1/+133
| | | | | | | | | | | | | | possible sets of x86 prefixes. This patch is the first step to close PR7709 and PR17697. There will be next patch(es) to close relative PRs. Differential Revision: https://reviews.llvm.org/D36788 M lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp M lib/Target/X86/Disassembler/X86DisassemblerDecoder.h A test/MC/Disassembler/X86/prefixes-i386.s A test/MC/Disassembler/X86/prefixes-x86_64.s M test/MC/Disassembler/X86/prefixes.txt llvm-svn: 311882
* [X86] Add nopq instruction which is a rex encoded version of nopl for gas ↵Craig Topper2017-07-221-0/+6
| | | | | | compatibility. llvm-svn: 308818
* [X86] Add register form of NOPL and NOPW for assembler/disassembler.Craig Topper2017-07-221-0/+6
| | | | | | Fixes PR32805. llvm-svn: 308817
* [X86] Adding vpopcntd and vpopcntq instructionsOren Ben Simhon2017-05-251-0/+23
| | | | | | | | | AVX512_VPOPCNTDQ is a new feature set that was published by Intel. The patch represents the LLVM side of the addition of two new intrinsic based instructions (vpopcntd and vpopcntq). Differential Revision: https://reviews.llvm.org/D33169 llvm-svn: 303858
* [X86][LWP] Add llvm support for LWP instructions (reapplied).Simon Pilgrim2017-05-032-0/+42
| | | | | | | | | | This patch adds support for the the LightWeight Profiling (LWP) instructions which are available on all AMD Bulldozer class CPUs (bdver1 to bdver4). Reapplied - this time without changing line endings of existing files. Differential Revision: https://reviews.llvm.org/D32769 llvm-svn: 302041
* Revert rL302028 due to accidental line ending changes.Simon Pilgrim2017-05-032-42/+0
| | | | llvm-svn: 302038
* [X86][LWP] Add llvm support for LWP instructions.Simon Pilgrim2017-05-032-0/+42
| | | | | | | | This patch adds support for the the LightWeight Profiling (LWP) instructions which are available on all AMD Bulldozer class CPUs (bdver1 to bdver4). Differential Revision: https://reviews.llvm.org/D32769 llvm-svn: 302028
* [X86][SSE2] Fix asm string for movq (Move Quadword) instruction.Ayman Musa2017-04-261-4/+4
| | | | | | | | Replace "mov{d|q}" with "movq". Differential Revision: https://reviews.llvm.org/D32220 llvm-svn: 301386
* [X86] Clzero intrinsic and its addition under znver1Craig Topper2017-02-091-0/+3
| | | | | | | | | | | | | | | | | This patch does the following. 1. Adds an Intrinsic int_x86_clzero which works with __builtin_ia32_clzero 2. Identifies clzero feature using cpuid info. (Function:8000_0008, Checks if EBX[0]=1) 3. Adds the clzero feature under znver1 architecture. 4. The custom inserter is added in Lowering. 5. A testcase is added to check the intrinsic. 6. The clzero instruction is added to assembler test. Patch by Ganesh Gopalasubramanian with a couple formatting tweaks, a disassembler test, and using update_llc_test.py from me. Differential revision: https://reviews.llvm.org/D29385 llvm-svn: 294558
* [X86] Remove PCOMMIT instruction support since Intel has deprecated this ↵Craig Topper2017-02-081-3/+0
| | | | | | | | instruction with no plans to release products with it. Intel's documentation for the deprecation https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction llvm-svn: 294405
* [X86] Fix printing of sha256rnds2 to include the implicit %xmm0 argument.Craig Topper2017-02-051-2/+2
| | | | llvm-svn: 294132
* [X86][Disassembler] Added SALC instructionChris Ray2017-01-291-790/+793
| | | | | | | | | | | | Reviewers: joe.abbey, craig.topper Reviewed By: craig.topper Subscribers: majnemer, llvm-commits Differential Revision: https://reviews.llvm.org/D29201 llvm-svn: 293447
* [X86] Adding FFREEP instruction.Chris Ray2017-01-271-1037/+1061
| | | | | | | | | | | | | | Summary: Small change to get the FREEP instruction to decode properly. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29193 llvm-svn: 293314
* [AVX-512] Teach the disassembler about all of the EVEX gather and scatter ↵Craig Topper2017-01-161-0/+95
| | | | | | instructions. llvm-svn: 292094
* [AVX-512] Fix a disassembler failure for AVX-512 vcmpss/vcmpsd with an ↵Craig Topper2016-11-131-0/+31
| | | | | | | | immediate larger than 32. Fix the same bug with VLX vcmpps/vcmppd. Fixes PR24941. llvm-svn: 286775
* Add new flag and intrinsic support for MWAITX and MONITORX instructionsAshutosh Nema2016-05-182-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: MONITORX/MWAITX instructions provide similar capability to the MONITOR/MWAIT pair while adding a timer function, such that another termination of the MWAITX instruction occurs when the timer expires. The presence of the MONITORX and MWAITX instructions is indicated by CPUID 8000_0001, ECX, bit 29. The MONITORX and MWAITX instructions are intercepted by the same bits that intercept MONITOR and MWAIT. MONITORX instruction establishes a range to be monitored. MWAITX instruction causes the processor to stop instruction execution and enter an implementation-dependent optimized state until occurrence of a class of events. Opcode of MONITORX instruction is "0F 01 FA". Opcode of MWAITX instruction is "0F 01 FB". These opcode information is used in adding tests for the disassembler. These instructions are enabled for AMD's bdver4 architecture. Patch by Ganesh Gopalasubramanian! Reviewers: echristo, craig.topper, RKSimon Subscribers: RKSimon, joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D19795 llvm-svn: 269911
* AVX512F: Add GATHER/SCATTER assembler Intel syntax tests for knl/skx/avx . ↵Igor Breger2016-02-251-2/+2
| | | | | | | | Change memory operand parser handling. Differential Revision: http://reviews.llvm.org/D17564 llvm-svn: 261862
* [X86] Add some missing reversed forms of XOP instructions.Craig Topper2016-02-201-0/+9
| | | | llvm-svn: 261417
* [AVX-512] Fix test case update missed in r257299.Craig Topper2016-01-111-1/+1
| | | | llvm-svn: 257303
* [llvm-mc] Ignore opcode size prefix in 64-bit CALL disassemblyVedant Kumar2015-08-261-0/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a fix for disassembling unusual instruction sequences in 64-bit mode w.r.t the CALL rel16 instruction. It might be desirable to move the check somewhere else, but it essentially mimics the special case handling with JCXZ in 16-bit mode. The current behavior accepts the opcode size prefix and causes the call's immediate to stop disassembling after 2 bytes. When debugging sequences of instructions with this pattern, the disassembler output becomes extremely unreliable and essentially useless (if you jump midway into what lldb thinks is a unified instruction, you'll lose %rip). So we ignore the prefix and consume all 4 bytes when disassembling a 64-bit mode binary. Note: in Vol. 2A 3-99 the Intel spec states that CALL rel16 is N.S. N.S. is defined as: Indicates an instruction syntax that requires an address override prefix in 64-bit mode and is not supported. Using an address override prefix in 64-bit mode may result in model-specific execution behavior. (Vol. 2A 3-7) Since 0x66 is an operand override prefix we should be OK (although we may want to warn about 0x67 prefixes to 0xe8). On the CPUs I tested with, they all ignore the 0x66 prefix in 64-bit mode. Patch by Matthew Barney! Differential Revision: http://reviews.llvm.org/D9573 llvm-svn: 246038
* [X86]: Correctly sign-extend 16-bit immediate in CALL instruction.Douglas Katzman2015-06-263-0/+11
| | | | | | | | Patch by Matthew Barney. Thanks! Differential Revision: http://reviews.llvm.org/D9514 llvm-svn: 240795
* [X86] Fix PR23271 - RIP-relative decoding bug in disassembler.Douglas Katzman2015-05-131-0/+38
| | | | | | Differential Revision: http://reviews.llvm.org/D9110 llvm-svn: 237310
* AVX-512: Added all forms of FP compare instructions for KNL and SKX.Elena Demikhovsky2015-05-071-1/+1
| | | | | | | | Added intrinsics for the instructions. CC parameter of the intrinsics was changed from i8 to i32 according to the spec. By Igor Breger (igor.breger@intel.com) llvm-svn: 236714
* Fix the operand encoding in the test instruction.Rafael Espindola2015-03-311-1/+1
| | | | | | Fixes pr22995. llvm-svn: 233686
* [X86] Fix diassembler crash on AVX512 cmpps/cmppd with immediate that ↵Craig Topper2015-03-021-0/+3
| | | | | | doesn't fit in 5-bits. Fixes PR22743. llvm-svn: 230924
* [X86] Add some missing redundant MMX and SSE encodings for disassembler.Craig Topper2015-02-221-0/+21
| | | | llvm-svn: 230165
* [X86] Add support for parsing and printing the mnemonic aliases for the XOP ↵Craig Topper2015-02-131-0/+6
| | | | | | VPCOM instructions. llvm-svn: 229078
* [X86] Add GETSEC instruction.Craig Topper2015-02-071-0/+3
| | | | llvm-svn: 228514
* [X86] Add assembler and disassembler test cases for clflushopt, clwb, ↵Craig Topper2015-02-061-0/+21
| | | | | | pcommit, xsaves, xrstors, xsavec llvm-svn: 228385
* [X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T ↵Craig Topper2015-02-031-3/+3
| | | | | | syntax. Also make them the default output. llvm-svn: 227963
* [X86] Teach disassembler to handle illegal immediates on AVX512 integer ↵Craig Topper2015-01-281-0/+27
| | | | | | compare instructions. llvm-svn: 227302
* [X86] Convert all the i8imm used by SSE and AVX instructions to u8imm.Craig Topper2015-01-211-1/+1
| | | | | | This makes the assembler check their size and removes a hack from the disassembler to avoid sign extending the immediate. llvm-svn: 226645
* [X86] Don't print 'dword ptr' or 'qword ptr' on the operand to some of the ↵Craig Topper2015-01-083-0/+47
| | | | | | LEA variants in Intel syntax. The memory operand is inherently unsized. llvm-svn: 225432
* [X86] Add OpSize32 to XBEGIN_4. Add XBEGIN_2 with OpSize16.Craig Topper2015-01-061-0/+3
| | | | | | Requires new AsmParserOperand types that detect 16-bit and 32/64-bit mode so that we choose the right instruction based on default sizing without predicates. This is necessary since predicates mess up the disassembler table building. llvm-svn: 225256
* [X86] Disassembler support for move to/from %rax with a 32-bit memory offset ↵Craig Topper2015-01-032-2/+14
| | | | | | is REX.W and AdSize prefix are both present. llvm-svn: 225099
* [X86] Make the instructions that use AdSize16/32/64 co-exist together ↵Craig Topper2015-01-021-16/+16
| | | | | | | | | | without using mode predicates. This is necessary to allow the disassembler to be able to handle AdSize32 instructions in 64-bit mode when address size prefix is used. Eventually we should probably also support 'addr32' and 'addr16' in the assembler to override the address size on some of these instructions. But for now we'll just use special operand types that will lookup the current mode size to select the right instruction. llvm-svn: 225075
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