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* Add Ivy Bridge 16-bit floating point conversion instructions for the X86 ↵Craig Topper2011-10-092-8/+56
| | | | | | disassembler. llvm-svn: 141505
* Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.Craig Topper2011-10-071-0/+24
| | | | llvm-svn: 141358
* Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT.Craig Topper2011-10-072-0/+18
| | | | llvm-svn: 141354
* Add support in the disassembler for ignoring the L-bit on certain VEX ↵Craig Topper2011-10-042-0/+54
| | | | | | instructions. Mark instructions that have this behavior. Fixes PR10676. llvm-svn: 141065
* Add support for MOVBE and RDRAND instructions for the assembler and ↵Craig Topper2011-10-032-0/+45
| | | | | | disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. llvm-svn: 141007
* Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to ↵Craig Topper2011-10-032-0/+6
| | | | | | registers xmm8-xmm15 outside 64-bit mode. llvm-svn: 140997
* Test updates that were supposed to go with r140993.Craig Topper2011-10-031-4/+4
| | | | llvm-svn: 140994
* Fix some Intel syntax disassembly issues with instructions that implicitly ↵Craig Topper2011-10-023-0/+168
| | | | | | use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. llvm-svn: 140974
* Special case disassembler handling of REX.B prefix on NOP instruction to ↵Craig Topper2011-10-021-0/+3
| | | | | | decode as XCHG R8D, EAX instead. Fixes PR10344. llvm-svn: 140971
* Fix disassembling of INVEPT and INVVPID to take operandsCraig Topper2011-10-012-0/+11
| | | | llvm-svn: 140955
* Fix disassembler handling of CRC32 which is an odd instruction that uses ↵Craig Topper2011-10-012-0/+15
| | | | | | 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. llvm-svn: 140954
* Fix VEX decoding in i386 mode. Fixes PR11008.Craig Topper2011-09-261-0/+289
| | | | llvm-svn: 140515
* Don't allow 32-bit only instructions to be disassembled in 64-bit mode. ↵Craig Topper2011-09-231-7/+4
| | | | | | Fixes part of PR10700. llvm-svn: 140370
* Fix register printing in disassembling of push/pop of segment registers and ↵Craig Topper2011-09-221-0/+12
| | | | | | in/out in Intel syntax mode. Fixes PR10960 llvm-svn: 140299
* Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND ↵Craig Topper2011-09-141-0/+18
| | | | | | from being recognized by disassembler. llvm-svn: 139691
* Make disassembling of VBLEND* print immediate as a XMM/YMM register name. ↵Craig Topper2011-09-141-0/+3
| | | | | | Fixes PR10917. llvm-svn: 139690
* Add test case for PR10851.Craig Topper2011-09-141-0/+4
| | | | llvm-svn: 139689
* Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from ↵Craig Topper2011-09-131-12/+48
| | | | | | being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. llvm-svn: 139588
* Fix disassembling of one of the register/register forms of ↵Craig Topper2011-09-111-0/+60
| | | | | | MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877. llvm-svn: 139486
* Fix disassembling of reverse register/register forms of ↵Craig Topper2011-09-111-0/+12
| | | | | | ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. llvm-svn: 139485
* Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP ↵Craig Topper2011-09-111-0/+3
| | | | | | disassembling to ignore OpSize and REX.W. llvm-svn: 139484
* Add disassembler test for Intel syntax. Tests r139353.Craig Topper2011-09-091-0/+13
| | | | llvm-svn: 139356
* Change X86 disassembly to print immediates values as signed by default. SpecialKevin Enderby2011-09-021-0/+56
| | | | | | case those instructions that the immediate is not sign-extend. radr://8795217 llvm-svn: 139028
* Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.Kevin Enderby2011-09-021-0/+3
| | | | llvm-svn: 139014
* Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form ↵Craig Topper2011-09-021-0/+3
| | | | | | from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806. llvm-svn: 138997
* Add vvvv support to disassembling of instructions with MRMDestMem and ↵Craig Topper2011-08-301-0/+3
| | | | | | MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807. llvm-svn: 138795
* Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217Kevin Enderby2011-08-291-0/+3
| | | | llvm-svn: 138771
* Fix disassembling of VCVTSD2SICraig Topper2011-08-261-0/+9
| | | | llvm-svn: 138623
* Give ATTR_VEX higher priority when generating the disassembler context ↵Craig Topper2011-08-251-0/+3
| | | | | | table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678. llvm-svn: 138552
* Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be ↵Craig Topper2011-08-251-0/+6
| | | | | | disassembled. Fixes PR10723. llvm-svn: 138551
* Add TB encoding to VEX versions of SSE fp logical operations to fix disassemblerCraig Topper2011-08-191-0/+6
| | | | llvm-svn: 138034
* Make the disassembler able to disassemble a bunch of instructions with names ↵Eli Friedman2011-07-161-0/+26
| | | | | | in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873. llvm-svn: 135337
* Basic sanity checks to ensure that 2- and 3-byteSean Callanan2011-03-151-0/+6
| | | | | | | | VEX prefixes are working for triadic AVX instructions. This concludes the patch set to enable AVX support for the X86 disassebler. llvm-svn: 127647
* Fixed a bug in the enhanced disassembler that causedSean Callanan2011-02-231-0/+2
| | | | | | | | it to ignore valid uses of FS and GS as additional base registers in address computations. Added a test case for this. llvm-svn: 126302
* Added a testcase for the enhanced disassembly bugSean Callanan2011-02-221-0/+4
| | | | | | | fixed in r126147, where a field in the X86 decode structure was being read as bits, not bytes. llvm-svn: 126182
* Correctly disassemble truncated asm.Rafael Espindola2011-01-061-0/+4
| | | | | | Patch by Richard Simth. llvm-svn: 122962
* Segregate tests by target.Dale Johannesen2010-11-142-0/+74
llvm-svn: 119050
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