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* added basic support for Intel ADX instructionsKay Tiong Khoo2013-02-142-0/+36
| | | | | | -feature flag, instructions definitions, test cases llvm-svn: 175196
* added test cases for r174920 (prefetch disassembly)Kay Tiong Khoo2013-02-121-0/+6
| | | | llvm-svn: 174979
* *fixed disassembly of some i386 system insts with intel syntaxKay Tiong Khoo2013-02-111-0/+13
| | | | | | *added file for test cases for i386 intel syntax llvm-svn: 174900
* Fix suffix handling for parsing and printing of cvtsi2ss, cvtsi2sd, ↵Craig Topper2013-01-062-10/+10
| | | | | | | | | | | cvtss2si, cvttss2si, cvtsd2si, and cvttsd2si to match gas behavior. cvtsi2* should parse with an 'l' or 'q' suffix or no suffix at all. No suffix should be treated the same as 'l' suffix. Printing should always print a suffix. Previously we didn't parse or print an 'l' suffix. cvtt*2si/cvt*2si should parse with an 'l' or 'q' suffix or not suffix at all. No suffix should use the destination register size to choose encoding. Printing should not print a suffix. Original 'l' suffix issue with cvtsi2* pointed out by Michael Kuperstein. llvm-svn: 171668
* Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky2012-12-191-10/+0
| | | | llvm-svn: 170578
* Added a option to the disassembler to print immediates as hex.Kevin Enderby2012-12-051-0/+10
| | | | | | | | | | | | | | | | | | | | This is for the lldb team so most of but not all of the values are to be printed as hex with this option. Some small values like the scale in an X86 address were requested to printed in decimal without the leading 0x. There may be some tweaks need to places that may still be in decimal that they want in hex. Specially for arm. I made my best guess. Any tweaks from here should be simple. I also did the best I know now with help from the C++ gurus creating the cleanest formatImm() utility function and containing the changes. But if someone has a better idea to make something cleaner I'm all ears and game for changing the implementation. rdar://8109283 llvm-svn: 169393
* Make this test less sensitive.Eli Bendersky2012-11-261-4/+4
| | | | | | | It currently assumes register numbering and any harmless change in the X86 register naming makes it fail. It's enough to match the register names. llvm-svn: 168632
* Add support for annotated disassembly output for X86 and arm.Kevin Enderby2012-10-221-0/+6
| | | | | | | | | | | Per the October 12, 2012 Proposal for annotated disassembly output sent out by Jim Grosbach this set of changes implements this for X86 and arm. The llvm-mc tool now has a -mdis option to produced the marked up disassembly and a couple of small example test cases have been added. rdar://11764962 llvm-svn: 166445
* Make l/q suffixes on AVX forms of scalar convert instructions consistent ↵Craig Topper2012-07-262-8/+8
| | | | | | with their non-AVX forms. llvm-svn: 160775
* Make x86 asm parser to check for xmm vs ymm for index register in gather ↵Craig Topper2012-07-181-0/+5
| | | | | | instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. llvm-svn: 160420
* Reverse assembler/disassembler operand order for gather instructions.Craig Topper2012-07-101-8/+8
| | | | llvm-svn: 159983
* Convert the uses of '|&' to use '2>&1 |' instead, which works on oldChandler Carruth2012-07-024-4/+4
| | | | | | | | | | versions of Bash. In addition, I can back out the change to the lit built-in shell test runner to support this. This should fix the majority of fallout on Darwin, but I suspect there will be a few straggling issues. llvm-svn: 159544
* Convert all tests using TCL-style quoting to use shell-style quoting.Chandler Carruth2012-07-022-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This was done through the aid of a terrible Perl creation. I will not paste any of the horrors here. Suffice to say, it require multiple staged rounds of replacements, state carried between, and a few nested-construct-parsing hacks that I'm not proud of. It happens, by luck, to be able to deal with all the TCL-quoting patterns in evidence in the LLVM test suite. If anyone is maintaining large out-of-tree test trees, feel free to poke me and I'll send you the steps I used to convert things, as well as answer any painful questions etc. IRC works best for this type of thing I find. Once converted, switch the LLVM lit config to use ShTests the same as Clang. In addition to being able to delete large amounts of Python code from 'lit', this will also simplify the entire test suite and some of lit's architecture. Finally, the test suite runs 33% faster on Linux now. ;] For my 16-hardware-thread (2x 4-core xeon e5520): 36s -> 24s llvm-svn: 159525
* X86: add more GATHER intrinsics in LLVMManman Ren2012-06-291-1/+19
| | | | | | | | | | | | | | | Corrected type for index of llvm.x86.avx2.gather.d.pd.256 from 256-bit to 128-bit. Corrected types for src|dst|mask of llvm.x86.avx2.gather.q.ps.256 from 256-bit to 128-bit. Support the following intrinsics: llvm.x86.avx2.gather.d.q, llvm.x86.avx2.gather.q.q llvm.x86.avx2.gather.d.q.256, llvm.x86.avx2.gather.q.q.256 llvm.x86.avx2.gather.d.d, llvm.x86.avx2.gather.q.d llvm.x86.avx2.gather.d.d.256, llvm.x86.avx2.gather.q.d.256 llvm-svn: 159402
* X86: add GATHER intrinsics (AVX2) in LLVMManman Ren2012-06-261-0/+6
| | | | | | | | | | | | Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. llvm-svn: 159221
* Add intrinsics, code gen, assembler and disassembler support for the SSE4a ↵Benjamin Kramer2012-05-292-0/+36
| | | | | | | | | | | extrq and insertq instructions. This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. llvm-svn: 157634
* Missed some register numbers.Benjamin Kramer2012-04-271-3/+3
| | | | llvm-svn: 155706
* Update edis test for r155704.Benjamin Kramer2012-04-271-1/+1
| | | | llvm-svn: 155705
* Add -disassemble support for -show-inst and -show-encode capability llvm-mc. ↵Richard Barton2012-04-161-1/+1
| | | | | | | | Also refactor so all MC paraphernalia are created once for all uses as much as possible. The test change is to account for the fact that the default disassembler behaviour has changed with regards to specifying the assembly syntax to use. llvm-svn: 154809
* Add retw and lretw instructions. Also, fix Intel syntax parsing for allCharles Davis2012-04-111-0/+6
| | | | | | ret instructions. llvm-svn: 154468
* Add the tests that were supposed to go with r153935 that I forgot svn addCraig Topper2012-04-062-0/+73
| | | | llvm-svn: 154165
* Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.Craig Topper2012-04-031-0/+12
| | | | llvm-svn: 153935
* Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnuEli Bendersky2012-03-251-8/+1
| | | | | | | | | | | | | | * Removed test/lib/llvm.exp - it is no longer needed * Deleted the dg.exp reading code from test/lit.cfg. There are no dg.exp files left in the test suite so this code is no longer required. test/lit.cfg is now much shorter and clearer * Removed a lot of duplicate code in lit.local.cfg files that need access to the root configuration, by adding a "root" attribute to the TestingConfig object. This attribute is dynamically computed to provide the same information as was previously provided by the custom getRoot functions. * Documented the config.root attribute in docs/CommandGuide/lit.pod llvm-svn: 153408
* Change the second line of the test added for r152414 to use CHECK-NEXT.Kevin Enderby2012-03-121-1/+1
| | | | | | Suggestion by Bill Wendling! llvm-svn: 152582
* Fix disasm of iret, sysexit, and sysret when displayed with Intel syntax.Bill Wendling2012-03-101-0/+22
| | | | | | Patch by Kay Tiong Khoo! llvm-svn: 152487
* Fix the x86 disassembler to at least print the lock prefix if it is the firstKevin Enderby2012-03-091-0/+5
| | | | | | | prefix. Added a FIXME to remind us this still does not work when it is not the first prefix. llvm-svn: 152414
* X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by ↵Craig Topper2012-02-272-0/+11
| | | | | | Kay Tiong Khoo. llvm-svn: 151510
* Add vmfunc instruction to X86 assembler and disassembler.Craig Topper2012-02-192-0/+6
| | | | llvm-svn: 150899
* Add X86 assembler and disassembler support for AMD SVM instructions. ↵Craig Topper2012-02-182-0/+48
| | | | | | Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. llvm-svn: 150873
* Replace all instances of dg.exp file with lit.local.cfg, since all tests are ↵Eli Bendersky2012-02-162-6/+13
| | | | | | | | run with LIT now and now Dejagnu. dg.exp is no longer needed. Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches. llvm-svn: 150664
* Add disassembler support for VPERMIL2PD and VPERMIL2PS.Craig Topper2011-12-301-2/+5
| | | | llvm-svn: 147368
* Add FMA4 instructions to disassembler.Craig Topper2011-12-301-0/+6
| | | | llvm-svn: 147367
* Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 ↵Craig Topper2011-12-291-0/+12
| | | | | | instructions. llvm-svn: 147353
* Expose FMA3 instructions to the disassembler.Craig Topper2011-12-291-0/+24
| | | | llvm-svn: 147351
* Add X86 SARX, SHRX, and SHLX instructions.Craig Topper2011-10-232-0/+54
| | | | llvm-svn: 142779
* Add X86 RORX instructionCraig Topper2011-10-232-0/+18
| | | | llvm-svn: 142741
* Add X86 MULX instruction for disassembler.Craig Topper2011-10-232-0/+24
| | | | llvm-svn: 142738
* Rename PEXTR to PEXT. Add intrinsics for BMI instructions.Craig Topper2011-10-192-6/+6
| | | | llvm-svn: 142480
* Add X86 PEXTR and PDEP instructions.Craig Topper2011-10-162-0/+36
| | | | llvm-svn: 142141
* Add X86 BZHI instruction as well as BMI2 feature detection.Craig Topper2011-10-162-0/+18
| | | | llvm-svn: 142122
* Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, ↵Craig Topper2011-10-162-0/+6
| | | | | | VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. llvm-svn: 142117
* Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand ↵Craig Topper2011-10-162-0/+18
| | | | | | 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen llvm-svn: 142105
* Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work ↵Craig Topper2011-10-152-0/+27
| | | | | | because these are the first VEX encoded instructions to use the reg field as an opcode extension. llvm-svn: 142082
* Add X86 ANDN instruction. Including instruction selection.Craig Topper2011-10-142-0/+24
| | | | llvm-svn: 141947
* Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 ↵Craig Topper2011-10-142-0/+15
| | | | | | processor which is gcc's name for Haswell. llvm-svn: 141939
* Revert r141854 because it was causing failures:Bill Wendling2011-10-132-15/+0
| | | | | | | | | | | | | | | http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101 --- Reverse-merging r141854 into '.': U test/MC/Disassembler/X86/x86-32.txt U test/MC/Disassembler/X86/simple-tests.txt D test/CodeGen/X86/bmi.ll U lib/Target/X86/X86InstrInfo.td U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86.td U lib/Target/X86/X86Subtarget.h llvm-svn: 141857
* Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 ↵Craig Topper2011-10-132-0/+15
| | | | | | processor which is gcc's name for Haswell. llvm-svn: 141854
* Add X86 LZCNT instruction. Including instruction selection support.Craig Topper2011-10-112-0/+15
| | | | llvm-svn: 141651
* Fix disassembling of popcntw. Also remove some code that says it accounts ↵Craig Topper2011-10-112-0/+15
| | | | | | for 64BIT_REXW_XD not existing, but it does exist. llvm-svn: 141642
* Insert dummy ED table entries for pseudo-instructions.Jakob Stoklund Olesen2011-10-101-0/+4
| | | | | | | | | | The table is indexed by opcode, so simply removing pseudo-instructions creates a wrong mapping from opcode to table entry. Add a test case for xorps which has a very high opcode that exposes this problem. llvm-svn: 141562
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