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* [X86] Update disassembler tests for absolute move instructions to check the ↵Craig Topper2014-12-311-37/+37
| | | | | | encodings. This provides testing for r225036. 64-bit mode is still broken. llvm-svn: 225037
* Testcases for r224939.Craig Topper2014-12-301-0/+17
| | | | llvm-svn: 224976
* [X86] Add the debug registers DR8-DR15 so we can assemble and disassemble ↵Craig Topper2014-12-261-0/+2
| | | | | | references to them. llvm-svn: 224862
* [X86] Don't fail disassembly if REX.R/REX.B is used on an MMX register. ↵Craig Topper2014-12-261-0/+9
| | | | | | Similar fix to not fail to disassembler CR9-CR15 references. llvm-svn: 224861
* Teach disassembler to handle illegal immediates on (v)cmpps/pd/ss/sd ↵Craig Topper2014-12-262-10/+9
| | | | | | instructions. Instead of rejecting we'll just generate the _alt forms that don't try to alter the mnemonic. While I'm here, merge some common code in the Instruction printers for the condition code replacement and fix the mask on SSE to be 3-bits instead of 4. llvm-svn: 224846
* AVX-512: Fixed encoding of VPBROADCASTM and added SKX forms of this instructionElena Demikhovsky2014-10-261-1/+8
| | | | llvm-svn: 220638
* [X86] Fix a bug where the disassembler was ignoring the VEX.W bit in 32-bit ↵Craig Topper2014-10-071-0/+3
| | | | | | | | | | mode for certain instructions it shouldn't. Unfortunately, this isn't easy to fix since there's no simple way to figure out from the disassembler tables whether the W-bit is being used to select a 64-bit GPR or if its a required part of the opcode. The fix implemented here just looks for "64" in the instruction name and ignores the W-bit in 32-bit mode if its present. Fixes PR21169. llvm-svn: 219194
* [X86] AVX512: Add disassembler support for compressed displacementAdam Nemet2014-07-171-0/+39
| | | | | | | | | | | | There are two parts here. First is to modify tablegen to adjust the encoding type ENCODING_RM with the scaling factor. The second is to use the new encoding types to compute the correct displacement in the decoder. Fixes <rdar://problem/17608489> llvm-svn: 213281
* [Disasm][AVX512] Implement decoding of top bit for non-destructive reg fieldsAdam Nemet2014-06-241-0/+6
| | | | | | | | | V' bit in the P2 byte of the EVEX prefix provides the top bit of the NDD and NDS register fields. This was simply not used in the decoder until now. Fixes <rdar://problem/17402661> llvm-svn: 211565
* llvm-mc: Add option for prefering hex format disassembly.Jim Grosbach2014-06-112-4/+4
| | | | | | | | | Previously there was a separate mode entirely (--hdis vs. --disassemble). It makes a bit more sense for the immediate printing style to be a flag for --disassmeble rather than an entirely different thing. llvm-svn: 210700
* Reduce verbiage of lit.local.cfg filesAlp Toker2014-06-091-2/+1
| | | | | | We can just split targets_to_build in one place and make it immutable. llvm-svn: 210496
* X86Disassembler - fixed a bug in immediate printElena Demikhovsky2014-04-231-0/+4
| | | | llvm-svn: 206953
* [X86] Add disassembler support for the 0x0f 0x7f form of movq %mm, %mm.Craig Topper2014-04-171-0/+3
| | | | llvm-svn: 206447
* Test case for r204305.Craig Topper2014-03-201-0/+4
| | | | llvm-svn: 204316
* Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of ↵Craig Topper2014-02-191-0/+56
| | | | | | 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. llvm-svn: 201641
* Fix diassembler handling of rex.b when mod=00/01/10 and bbb=101. Mod=00 ↵Craig Topper2014-02-171-0/+24
| | | | | | should ignore the base register entirely. Mod=01/10 should treat this as R13 plus displacment. Fixes PR18860. llvm-svn: 201507
* Add opcode extension forms of MOV8ri/MOV16ri/MOV32ri.Craig Topper2014-02-151-0/+9
| | | | llvm-svn: 201463
* [x86] Fix disassembly of MOV16ao16 et al.David Woodhouse2014-01-201-0/+86
| | | | | | | | | | The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It also turns out to have been unnecessary. The disassembler handles the AdSize prefix for itself, and doesn't care about the difference between (e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and don't worry about it. llvm-svn: 199654
* [x86] Fix 16-bit disassembly of JCXZ/JECXZDavid Woodhouse2014-01-201-2/+2
| | | | llvm-svn: 199653
* [x86] Rename MOVSD/STOSD/LODSD/OUTSD to MOVSL/STOSL/LODSL/OUTSLDavid Woodhouse2014-01-201-9/+9
| | | | | | | | The disassembler has a special case for 'L' vs. 'W' in its heuristic for checking for 32-bit and 16-bit equivalents. We could expand the heuristic, but better just to be consistent in using the 'L' suffix. llvm-svn: 199652
* [x86] Fix disassembly of callw instructionDavid Woodhouse2014-01-201-2/+2
| | | | | | | Not quite sure why this was marked isAsmParserOnly, but it means that the disassembler can't see it either. llvm-svn: 199651
* [x86] Fix 16-bit handling of OpSize bitDavid Woodhouse2014-01-201-0/+788
| | | | | | | | | | When disassembling in 16-bit mode the meaning of the OpSize bit is inverted. Instructions found in the IC_OPSIZE context will actually *not* have the 0x66 prefix, and instructions in the IC context will have the 0x66 prefix. Make use of the existing special-case handling for the 0x66 prefix being in the wrong place, to cope with this. llvm-svn: 199650
* Allow x86 mov instructions to/from memory with absolute address to be ↵Craig Topper2014-01-161-0/+3
| | | | | | encoded and disassembled with a segment override prefix. Fixes PR16962. llvm-svn: 199364
* Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are ↵Craig Topper2014-01-011-0/+12
| | | | | | really more like OrRegFrm so we don't need a difference since we can just mask bits. llvm-svn: 198278
* Add two fp test cases I missed in my previous commit.Craig Topper2013-12-311-0/+6
| | | | llvm-svn: 198269
* Add more X86 FP stack disassembler test cases.Craig Topper2013-12-312-324/+1031
| | | | llvm-svn: 198268
* Revert r198238 and add FP disassembler tests. It didn't work and I didn't ↵Craig Topper2013-12-311-0/+324
| | | | | | realized we had no FP disassembler test cases. llvm-svn: 198265
* AVX-512: decoder for AVX-512, made by Alexey Bader.Elena Demikhovsky2013-12-251-0/+59
| | | | llvm-svn: 198013
* Add disassembler support for SSE4.1 register/register form of PEXTRW. There ↵Craig Topper2013-10-141-0/+6
| | | | | | is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding. llvm-svn: 192566
* Remove some instructions that existed to provide aliases to the assembler. ↵Craig Topper2013-10-081-0/+6
| | | | | | Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. llvm-svn: 192171
* Remove some instructions that seem to only exist to trick the filtering ↵Craig Topper2013-10-072-0/+12
| | | | | | checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead. llvm-svn: 192090
* Add disassembler support for long encodings for INC/DEC in 32-bit mode.Craig Topper2013-10-072-1/+49
| | | | llvm-svn: 192086
* Add XOP disassembler support. Fixes PR13933.Craig Topper2013-10-031-0/+72
| | | | llvm-svn: 191874
* Add a few more FMA4 disassembler test cases to match the scalar set with ↵Craig Topper2013-09-301-0/+12
| | | | | | regards to combinations of L and W-bits. llvm-svn: 191650
* Various x86 disassembler fixes.Craig Topper2013-09-301-0/+36
| | | | | | | | | | | Add VEX_LIG to scalar FMA4 instructions. Use VEX_LIG in some of the inheriting checks in disassembler table generator. Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts. Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set. Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases. Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms. llvm-svn: 191649
* Fixing Intel format of the vshufpd instruction.Yunzhong Gao2013-09-271-0/+3
| | | | | | Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759 llvm-svn: 191481
* Add the remaining Intel SHA instructionsBen Langmuir2013-09-141-1/+37
| | | | | | | Also assembly/disassembly tests, and for sha256rnds2, aliases with an explicit xmm0 dependency. llvm-svn: 190754
* Partial support for Intel SHA Extensions (sha1rnds4)Ben Langmuir2013-09-121-0/+6
| | | | | | | | | Add basic assembly/disassembly support for the first Intel SHA instruction 'sha1rnds4'. Also includes feature flag, and test cases. Support for the remaining instructions will follow in a separate patch. llvm-svn: 190611
* Fixed a bug where diassembling an instruction that had a prefix would cause ↵Richard Mitton2013-08-301-0/+59
| | | | | | LLVM to identify a 1-byte instruction, but then upon querying it for that 1-byte instruction would cause an undefined opcode. llvm-svn: 189698
* First round of fixes for the x86 fixes for the x86 move accumulator from/to ↵Craig Topper2013-08-253-4/+70
| | | | | | | | | | | | | | memory offset instructions. -Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted. -x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size. -Intel syntax printing prints the ptr size and places brackets around the address immediate. Known remaining issues with these instructions: -Segment override prefix is not supported. PR16962 and PR16961. -Immediate size should be changed by address size prefix. llvm-svn: 189201
* [tests] Cleanup initialization of test suffixes.Daniel Dunbar2013-08-161-2/+0
| | | | | | | | | | | | | | | | | - Instead of setting the suffixes in a bunch of places, just set one master list in the top-level config. We now only modify the suffix list in a few suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py). - Aside from removing the need for a bunch of lit.local.cfg files, this enables 4 tests that were inadvertently being skipped (one in Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been XFAILED). - This commit also fixes a bunch of config files to use config.root instead of older copy-pasted code. llvm-svn: 188513
* Changed register names (and pointer keywords) to be lower case when using ↵Craig Topper2013-07-311-26/+26
| | | | | | | | Intel X86 assembler syntax. Patch by Richard Mitton. llvm-svn: 187476
* Don't let x86 asm printer use the no operand movsd alias. It should use the ↵Craig Topper2013-07-231-1/+1
| | | | | | normal movsl instead. llvm-svn: 186924
* Fix the move to/from accumulator register instructions that use a full 64-bitKevin Enderby2013-07-221-0/+30
| | | | | | | | absolute address encoded in the instruction. rdar://8612627 and rdar://14299221 llvm-svn: 186878
* Update the X86 disassembler to use xacquire and xrelease when appropriate.Kevin Enderby2013-06-201-1/+29
| | | | | | | | | | | | | | | | | This is a bit tricky as the xacquire and xrelease hints use the same bytes, 0xf2 and 0xf3, as the repne and rep prefixes. Fortunately llvm has different llvm MCInst Opcode enums for rep/xrelease and repne/xacquire. So to make this work a boolean was added the InternalInstruction struct as part of the Prefix state which is set with the added logic in readPrefixes() when decoding an instruction to determine if these prefix bytes are to be disassembled as xacquire or xrelease. Then we let the matcher pick the normal prefix instructionID and we change the Opcode after that when it is set into the MCInst being created. rdar://11019859 llvm-svn: 184490
* Add CLAC/STAC instruction encoding/decoding supportMichael Liao2013-04-111-0/+6
| | | | | | | As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. llvm-svn: 179266
* fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test casesKay Tiong Khoo2013-04-102-0/+18
| | | | llvm-svn: 179223
* x86 -- disassemble the REP/REPNE prefix when neededDave Zarzycki2013-03-251-0/+15
| | | | | | This fixes Apple bug: 13493622 llvm-svn: 177887
* Fixes disassembler crashes on 2013 Haswell RTM instructions.Kevin Enderby2013-03-111-0/+9
| | | | | | rdar://13318048 llvm-svn: 176828
* death to extra whitespaceKay Tiong Khoo2013-02-141-20/+20
| | | | llvm-svn: 175200
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