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* Add support for part-word atomics for PPCNemanja Ivanovic2015-03-101-2/+20
| | | | | | http://reviews.llvm.org/D8090#inline-67337 llvm-svn: 231843
* Add LLVM support for PPC cryptography builtinsNemanja Ivanovic2015-03-041-0/+36
| | | | | | Review: http://reviews.llvm.org/D7955 llvm-svn: 231285
* Add the following 64-bit vector integer arithmetic instructions added in POWER8:Kit Barton2015-03-031-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | vaddudm vsubudm vmulesw vmulosw vmuleuw vmulouw vmuluwm vmaxsd vmaxud vminsd vminud vcmpequd vcmpequd. vcmpgtsd vcmpgtsd. vcmpgtud vcmpgtud. vrld vsld vsrd vsrad Phabricator review: http://reviews.llvm.org/D7959 llvm-svn: 231115
* [PowerPC] Add support for the QPX vector instruction setHal Finkel2015-02-251-0/+383
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the QPX vector instruction set, which is used by the enhanced A2 cores on the IBM BG/Q supercomputers. QPX vectors are 256 bytes wide, holding 4 double-precision floating-point values. Boolean values, modeled here as <4 x i1> are actually also represented as floating-point values (essentially { -1, 1 } for { false, true }). QPX shares many features with Altivec and VSX, but is distinct from both of them. One major difference is that, instead of adding completely-separate vector registers, QPX vector registers are extensions of the scalar floating-point registers (lane 0 is the corresponding scalar floating-point value). The operations supported on QPX vectors mirrors that supported on the scalar floating-point values (with some additional ones for permutations and logical/comparison operations). I've been maintaining this support out-of-tree, as part of the bgclang project, for several years. This is not the entire bgclang patch set, but is most of the subset that can be cleanly integrated into LLVM proper at this time. Adding this to the LLVM backend is part of my efforts to rebase bgclang to the current LLVM trunk, but is independently useful (especially for codes that use LLVM as a JIT in library form). The assembler/disassembler test coverage is complete. The CodeGen test coverage is not, but I've included some tests, and more will be added as follow-up work. llvm-svn: 230413
* This patch adds the VSX logical instructions introduced in the Power ISA ↵Kit Barton2015-02-181-0/+9
| | | | | | | | | | 2.07. It also removes the added complexity that favors VMX versions of the three instructions. Phabricator review: http://reviews.llvm.org/D7616 Commiting on Nemanja's behalf. llvm-svn: 229694
* This change implements the following three logical vector operations:Kit Barton2015-02-091-0/+9
| | | | | | | | | | | | veqv (vector equivalence) vnand vorc I increased the AddedComplexity for these instructions to 500 to ensure they are generated instead of issuing other VSX instructions. Phabricator review: http://reviews.llvm.org/D7469 llvm-svn: 228580
* [PowerPC] Implement the vclz instructions for PWR8Bill Schmidt2015-02-051-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Patch by Kit Barton. Add the vector count leading zeros instruction for byte, halfword, word, and doubleword sizes. This is a fairly straightforward addition after the changes made for vpopcnt: 1. Add the correct definitions for the various instructions in PPCInstrAltivec.td 2. Make the CTLZ operation legal on vector types when using P8Altivec in PPCISelLowering.cpp Test Plan Created new test case in test/CodeGen/PowerPC/vec_clz.ll to check the instructions are being generated when the CTLZ operation is used in LLVM. Check the encoding and decoding in test/MC/PowerPC/ppc_encoding_vmx.s and test/Disassembler/PowerPC/ppc_encoding_vmx.txt respectively. llvm-svn: 228301
* [PowerPC] Implement the vpopcnt instructions for POWER8Bill Schmidt2015-02-031-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Patch by Kit Barton. Add the vector population count instructions for byte, halfword, word, and doubleword sizes. There are two major changes here: PPCISelLowering.cpp: Make CTPOP legal for vector types. PPCRegisterInfo.td: Added v2i64 to the VRRC register definition. This is needed for the doubleword variations of the integer ops that were added in P8. Test Plan Test the instruction vpcnt* encoding/decoding in ppc64-encoding-vmx.s Test the generation of the vpopcnt instructions for various vector data types. When adding the v2i64 type to the Vector Register set, I also needed to add the appropriate bit conversion patterns between v2i64 and the existing vector types. Testing for these conversions were also added in the test case by passing a different vector type as a parameter into the test functions. There is also a run step that will ensure the vpopcnt instructions are generated when the vsx feature is disabled. llvm-svn: 228046
* [PowerPC] Add assembler support for mcrfs and friendsHal Finkel2015-01-151-0/+18
| | | | | | | | | | Fill out our support for the floating-point status and control register instructions (mcrfs and friends). As it turns out, these are necessary for compiling src/test/harness_fp.h in TBB for PowerPC. Thanks to Raf Schietekat for reporting the issue! llvm-svn: 226070
* [PowerPC] Add support for the CMPB instructionHal Finkel2015-01-031-0/+3
| | | | | | | | | | | | | | Newer POWER cores, and the A2, support the cmpb instruction. This instruction compares its operands, treating each of the 8 bytes in the GPRs separately, returning a 'mask' result of 0 (for false) or -1 (for true) in each byte. Code generation support is added, in the form of a PPCISelDAGToDAG DAG-preprocessing routine, that recognizes patterns close to what the instruction computes (either exactly, or related by a constant masking operation), and generates the cmpb instruction (along with any necessary constant masking operation). This can be expanded if use cases arise. llvm-svn: 225106
* [PowerPC] Add asm support for cache-inhibited ld/st instructionsHal Finkel2014-11-301-0/+17
| | | | | | | | | Add assembler support for the fixed-point cache-inhibited load/store instructions. These are hypervisor-level only, so don't get too excited ;) Fixes PR21650. llvm-svn: 222976
* [PowerPC] Add the 'attn' instructionHal Finkel2014-11-251-0/+4
| | | | | | | | The attn instruction is not part of the Power ISA, but is documented in the A2 user manual, and is accepted by the GNU assembler for the A2 and the POWER4+. Reported as part of PR21650. llvm-svn: 222712
* [PowerPC] Add support for dcbtst and icbt (prefetch)Hal Finkel2014-08-231-0/+3
| | | | | | | | | | | | Adds code generation support for dcbtst (data cache prefetch for write) and icbt (instruction cache prefetch for read - Book E cores only). We still end up with a 'cannot select' error for the non-supported prefetch intrinsic forms. This will be fixed in a later commit. Fixes PR20692. llvm-svn: 216339
* Update disassembler test to check the full dccci/iccci form.Joerg Sonnenberger2014-08-091-4/+4
| | | | llvm-svn: 215283
* Add RFID instruction.Joerg Sonnenberger2014-08-071-0/+3
| | | | llvm-svn: 215105
* Add dci/ici instructions for PPC 476 and friends.Joerg Sonnenberger2014-08-051-0/+5
| | | | llvm-svn: 214864
* Add lswi / stswi for assembler use with a warning to not add patternsJoerg Sonnenberger2014-08-051-0/+5
| | | | | | for them. llvm-svn: 214862
* Add PPC 603's tlbld and tlbli instructions.Joerg Sonnenberger2014-08-041-0/+6
| | | | llvm-svn: 214825
* tlbre / tlbwe / tlbsx / tlbsx. variants for the PPC 4xx CPUs.Joerg Sonnenberger2014-08-041-0/+15
| | | | llvm-svn: 214784
* Add features for PPC 4xx and e500/e500mc instructions.Joerg Sonnenberger2014-08-043-10/+13
| | | | | | Move the test cases for them into separate files. llvm-svn: 214724
* tlbia supportJoerg Sonnenberger2014-08-021-0/+3
| | | | llvm-svn: 214640
* mfdcr / mtdcr supportJoerg Sonnenberger2014-08-021-0/+5
| | | | llvm-svn: 214639
* Don't use additional arguments for dss and friends to satisfy DSS_Form,Joerg Sonnenberger2014-08-021-0/+13
| | | | | | | | | when let can do the same thing. Keep the 64bit variants as codegen-only. While they have a different register class, the encoding is the same for 32bit and 64bit mode. Having both present would otherwise confuse the disassembler. llvm-svn: 214636
* Refactor TLBIVAX and add tlbsx.Joerg Sonnenberger2014-07-301-0/+2
| | | | llvm-svn: 214354
* Add rfdi and rfmci from the e500/e500mc ISA.Joerg Sonnenberger2014-07-301-0/+4
| | | | llvm-svn: 214339
* Add BookE's tlbre, tlbwe and tlbivax instructions.Joerg Sonnenberger2014-07-301-0/+7
| | | | llvm-svn: 214332
* Add BookE's wrtee and wrteei instructions.Joerg Sonnenberger2014-07-301-0/+7
| | | | llvm-svn: 214297
* Add rfci instruction.Joerg Sonnenberger2014-07-291-0/+2
| | | | llvm-svn: 214256
* Recognize BookE's mbar instruction.Joerg Sonnenberger2014-07-291-0/+3
| | | | llvm-svn: 214244
* Support move to/from segment register.Joerg Sonnenberger2014-07-291-0/+4
| | | | llvm-svn: 214234
* Add rfi instruction. Based on feedback by Ulrich Weigand.Joerg Sonnenberger2014-07-291-0/+2
| | | | llvm-svn: 214181
* Reduce verbiage of lit.local.cfg filesAlp Toker2014-06-091-2/+1
| | | | | | We can just split targets_to_build in one place and make it immutable. llvm-svn: 210496
* [PowerPC] Initial support for the VSX instruction setHal Finkel2014-03-131-0/+452
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | VSX is an ISA extension supported on the POWER7 and later cores that enhances floating-point vector and scalar capabilities. Among other things, this adds <2 x double> support and generally helps to reduce register pressure. The interesting part of this ISA feature is the register configuration: there are 64 new 128-bit vector registers, the 32 of which are super-registers of the existing 32 scalar floating-point registers, and the second 32 of which overlap with the 32 Altivec vector registers. This makes things like vector insertion and extraction tricky: this can be free but only if we force a restriction to the right register subclass when needed. A new "minipass" PPCVSXCopy takes care of this (although it could do a more-optimal job of it; see the comment about unnecessary copies below). Please note that, currently, VSX is not enabled by default when targeting anything because it is not yet ready for that. The assembler and disassembler are fully implemented and tested. However: - CodeGen support causes miscompiles; test-suite runtime failures: MultiSource/Benchmarks/FreeBench/distray/distray MultiSource/Benchmarks/McCat/08-main/main MultiSource/Benchmarks/Olden/voronoi/voronoi MultiSource/Benchmarks/mafft/pairlocalalign MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4 SingleSource/Benchmarks/CoyoteBench/almabench SingleSource/Benchmarks/Misc/matmul_f64_4x4 - The lowering currently falls back to using Altivec instructions far more than it should. Worse, there are some things that are scalarized through the stack that shouldn't be. - A lot of unnecessary copies make it past the optimizers, and this needs to be fixed. - Many more regression tests are needed. Normally, I'd fix these things prior to committing, but there are some students and other contributors who would like to work this, and so it makes sense to move this development process upstream where it can be subject to the regular code-review procedures. llvm-svn: 203768
* Add a disassembler to the PowerPC backendHal Finkel2013-12-198-0/+3991
The tests for the disassembler were adapted from the encoder tests, and for the most part, the output from the disassembler matches that encoder-test inputs. There are some places where more-informative mnemonics could be produced (notably for the branch instructions), and those cases are noted in the tests with FIXMEs. Future work includes: - Generating more-informative mnemonics when possible (this may also be done in the printer). - Remove the dependence on positional "numbered" operand-to-variable mapping (for both encoding and decoding). - Internally using 64-bit instruction variants in 64-bit mode (if this turns out to matter). llvm-svn: 197693
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