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* [mips] Fix aui/daui/dahi/dati for MIPSR6Simon Dardis2016-10-146-8/+9
| | | | | | | | | | | | For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 284218
* [mips] Add IAS support for dvp, evpSimon Dardis2016-10-136-0/+24
| | | | | | | | | | | | | These instructions were only defined for microMIPSR6 previously. Add definitions for MIPSR6, correct definitions for microMIPSR6, flag these instructions as having unmodelled side effects (they disable/enable virtual processors) and add missing disassember tests for microMIPSR6. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24291 llvm-svn: 284115
* Recommit: "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-0530-35/+91
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 283334
* Revert "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-0530-91/+35
| | | | | | | This reverts commit r282485 which contain two patches instead of one. llvm-svn: 283327
* [mips] Add rsqrt, recip for MIPSSimon Dardis2016-09-2730-35/+91
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 282485
* Revert "[mips] Fix aui/daui/dahi/dati for MIPSR6"Simon Dardis2016-09-166-9/+8
| | | | | | This reverts r281724. Still need dsanders to accept this. llvm-svn: 281726
* [mips] Fix aui/daui/dahi/dati for MIPSR6Simon Dardis2016-09-166-8/+9
| | | | | | | | | | | | For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: vkalintiris, dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 281724
* [mips][microMIPS] Implement DBITSWAP, DLSA and LWUPC and add tests for AUI ↵Hrvoje Varga2016-09-081-0/+4
| | | | | | | | instructions Differential Revision: https://reviews.llvm.org/D16452 llvm-svn: 280909
* [mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix ↵Hrvoje Varga2016-08-225-49/+57
| | | | | | | | disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
* [mips][microMIPS] Implement CFC1, CFC2, CTC1 and CTC2 instructionsHrvoje Varga2016-08-043-0/+12
| | | | | | Differential Revision: https://reviews.llvm.org/D22347 llvm-svn: 277719
* [mips][ias] Check '$rs = $rd' constraints when both registers are in AsmText.Daniel Sanders2016-07-272-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is one possible solution to the problem of ignoring constraints that Simon raised in D21473 but it's a bit of a hack. The integrated assembler currently ignores violations of the tied register constraints when the operands involved in a tie are both present in the AsmText. For example, 'dati $rs, $rt, $imm' with the '$rs = $rt' will silently replace $rt with $rs. So 'dati $2, $3, 1' is processed as if the user provided 'dati $2, $2, 1' without any diagnostic being emitted. This is difficult to solve properly because there are multiple parts of the matcher that are silently forcing these constraints to be met. Tied operands are rendered to instructions by cloning previously rendered operands but this is unnecessary because the matcher was already instructed to render the operand it would have cloned. This is also unnecessary because earlier code has already replaced the MCParsedOperand with the one it was tied to (so the parsed input is matched as if it were 'dati <RegIdx 2>, <RegIdx 2>, <Imm 1>'). As a result, it looks like fixing this properly amounts to a rewrite of the tied operand handling which affects all targets. This patch however, merely inserts a checking hook just before the substitution of MCParsedOperands and the Mips target overrides it. It's not possible to accurately check the registers are the same this early (because numeric registers haven't been bound to a register class yet) so it cheats a bit and checks that the tokens that produced the operand are lexically identical. This works because tied registers need to have the same register class but it does have a flaw. It will reject 'dati $4, $a0, 1' for violating the constraint even though $a0 ends up as the same register as $4. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D21994 llvm-svn: 276867
* [mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructionsHrvoje Varga2016-07-221-0/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D19906 llvm-svn: 276397
* [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and ↵Zlatko Buljan2016-07-114-0/+32
| | | | | | | | SWC2 instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D18824 llvm-svn: 275050
* [mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV ↵Hrvoje Varga2016-06-271-0/+7
| | | | | | | | instructions Differential Revision: http://reviews.llvm.org/D16625 llvm-svn: 273850
* [mips][micromips] Implement DCLO, DCLZ, DROTR, DROTR32 and DROTRV instructionsHrvoje Varga2016-06-161-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D16917 llvm-svn: 272876
* [mips][microMIPS] Add CodeGen support for AND*, OR16, OR*, XOR*, NOT16 and ↵Zlatko Buljan2016-06-154-8/+15
| | | | | | | | NOR instructions Differential Revision: http://reviews.llvm.org/D16719 llvm-svn: 272764
* [mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructionsHrvoje Varga2016-06-091-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D11798 llvm-svn: 272259
* [MIPS][LLVM-MC] Fix Disassemble of Negative OffsetSagar Thakur2016-05-245-126/+184
| | | | | | | | | | | Patch by Nitesh Jain. Summary: The type of Imm in MipsDisassembler.cpp was incorrect since SignExtend64 return int64_t type.As per the MIPSr6 doc ,the offset is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address hence “4” is added to the offset. The offset of some test case are update to reflect the changes due to “ + 4 ” offset and new test case for negative offset are added. Reviewers: dsanders, vkalintiris Differential Revision: http://reviews.llvm.org/D17540 llvm-svn: 270542
* [mips][microMIPS] Implement BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructionsZlatko Buljan2016-05-192-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D18352 llvm-svn: 270030
* [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions and add ↵Zlatko Buljan2016-05-182-0/+8
| | | | | | | | CodeGen support Differential Revision: http://reviews.llvm.org/D15418 llvm-svn: 269883
* [mips][microMIPS] Implement BEQZC and BNEZC instructionsZoran Jovanovic2016-05-171-0/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D15417 llvm-svn: 269755
* [mips][microMIPS][DSP] Implement BALIGN, BITREV, BPOSGE32, CMP*, CMPGDU*, ↵Zlatko Buljan2016-05-173-0/+27
| | | | | | | | CMPGU* and CMPU* instructions Differential Revision: http://reviews.llvm.org/D16182 llvm-svn: 269752
* [mips][microMIPS] Implement APPEND, BPOSGE32C, MODSUB, MULSA.W.PH and ↵Hrvoje Varga2016-05-133-0/+7
| | | | | | | | MULSAQ_S.W.PH instructions Differential Revision: http://reviews.llvm.org/D14117 llvm-svn: 269408
* Revert "[mips][microMIPS] Implement CFC*, CTC* and LDC* instructions"Hrvoje Varga2016-05-121-6/+0
| | | | | | This reverts commit r269176 as it caused test-suite failure. llvm-svn: 269287
* [mips][microMIPS] Implement CFC*, CTC* and LDC* instructionsHrvoje Varga2016-05-111-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D19713 llvm-svn: 269176
* [mips][micromips] Implement DSBH, DSHD, DSLL, DSLL32, DSLLV, DSRA, DSRA32 ↵Hrvoje Varga2016-05-111-0/+7
| | | | | | | | and DSRAV instructions Differential Revision: http://reviews.llvm.org/D16800 llvm-svn: 269169
* [mips][microMIPS] Implement LWP and SWP instructionsZlatko Buljan2016-05-092-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D10640 llvm-svn: 268896
* [mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructionsZlatko Buljan2016-05-061-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D15744 llvm-svn: 268714
* [mips][microMIPS] Add CodeGen support for microMIPSr6 ROTR and ROTRV and add ↵Zlatko Buljan2016-05-044-0/+24
| | | | | | | | tests for LL, SC, SYSCALL, ROTR, ROTRV, LWM32, SWM32 and MOVEP instructions Differential Revision: http://reviews.llvm.org/D19857 llvm-svn: 268491
* [mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, DSUB and DSUBU ↵Zlatko Buljan2016-04-271-0/+6
| | | | | | | | instructions Differential Revision: http://reviews.llvm.org/D16676 llvm-svn: 267694
* [mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, ↵Zlatko Buljan2016-04-272-0/+11
| | | | | | | | SRAV, SRL and SRLV instructions Differential Revision: http://reviews.llvm.org/D17989 llvm-svn: 267693
* [mips][microMIPS] Revert commit r267137Hrvoje Varga2016-04-251-4/+0
| | | | | | Commit r267137 was the reason for failing tests in LLVM test suite. llvm-svn: 267419
* [mips][microMIPS] Revert commit r266977Zlatko Buljan2016-04-254-24/+0
| | | | | | Commit r266977 was reason for failing LLVM test suite with error message: fatal error: error in backend: Cannot select: t17: i32 = rotr t2, t11 ... llvm-svn: 267418
* [mips][microMIPS] Revert commit r266861.Zoran Jovanovic2016-04-221-6/+0
| | | | | | Commit r266861 was the reason for failing tests in LLVM test suite. llvm-svn: 267166
* [mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructionsHrvoje Varga2016-04-221-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D19354 llvm-svn: 267137
* [mips][microMIPS] Implement DVP, EVP and JALRC.HB instructionsZlatko Buljan2016-04-222-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D18687 llvm-svn: 267114
* [mips][microMIPS] Implement ldpc instructionZoran Jovanovic2016-04-211-0/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D15009 llvm-svn: 266990
* [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructionsZlatko Buljan2016-04-212-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D18855 llvm-svn: 266980
* [mips][microMIPS] Implement LL, SC, MOVEP, ROTR, ROTRV and SYSCALL ↵Zlatko Buljan2016-04-214-0/+24
| | | | | | | | instructions and add tests for LWM32 and SWM32 Differential Revision: http://reviews.llvm.org/D19150 llvm-svn: 266977
* [mips][microMIPS] Implement BGEC, BGEUC, BLTC, BLTUC, BEQC and BNEC instructionsZoran Jovanovic2016-04-201-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D14206 llvm-svn: 266873
* [mips][microMIPS]Implement CFC*, CTC* and LDC* instructionsHrvoje Varga2016-04-201-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D18640 llvm-svn: 266861
* Summary:Simon Dardis2016-04-144-0/+8
| | | | | | | | | | Alias 'jic $reg, 0' to 'jrc $reg' and 'jialc $reg, 0' to 'jalrc $reg' like binutils. This patch was previous committed as r266055 as seemed to have caused some spurious test failures. They did not reappear after further local testing. llvm-svn: 266301
* [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, ↵Zlatko Buljan2016-04-131-4/+4
| | | | | | | | | | | | DDIVU and DMODU instructions Differential Revision: http://reviews.llvm.org/D17137 This patch was reverted after the revertion of dependant patch http://reviews.llvm.org/D17068. There was the problem with test-suite failure. The problem is hopefully solved with dependant patch so this patch is commited again. llvm-svn: 266179
* Revert "[mips] MIPSR6 Compact branch aliases"Simon Dardis2016-04-124-8/+0
| | | | | | | | This reverts commit r266055. ps4-buildslave2 is highlighting a failure. llvm-svn: 266061
* [mips] MIPSR6 Compact branch aliasesSimon Dardis2016-04-124-0/+8
| | | | | | | | | | | | Summary: Alias 'jic $reg, 0' to 'jrc $reg' and 'jialc $reg, 0' to 'jalrc $reg' like binutils. Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D18856 llvm-svn: 266055
* [mips][microMIPS] Add CodeGen support for ADD, ADDIU*, ADDU* and DADD* ↵Zlatko Buljan2016-04-081-0/+22
| | | | | | | | instructions Differential Revision: http://reviews.llvm.org/D16454 llvm-svn: 265772
* [mips][microMIPS] Revert commits r264245 and r264248.Zoran Jovanovic2016-04-021-4/+4
| | | | | | | Commit r264245 was the reason for failing tests in LLVM test suite. Commit r264248 depends on the first one. llvm-svn: 265249
* [mips][microMIPS] Implement MFC*, MFHC* and DMFC* instructionsZlatko Buljan2016-03-312-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D17334 llvm-svn: 265002
* [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, ↵Zlatko Buljan2016-03-241-4/+4
| | | | | | | | DDIVU and DMODU instructions Differential Revision: http://reviews.llvm.org/D17137 llvm-svn: 264248
* [mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructionsHrvoje Varga2016-03-242-0/+25
| | | | | | Differential Revision: http://reviews.llvm.org/D17328 llvm-svn: 264246
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