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* [mips] Move disassembler test (test_2r_msa64) into correct folder.Matheus Almeida2014-05-121-0/+3
| | | | llvm-svn: 208594
* [mips] Move disassembler test (Mips MSA test_vec) into correct folder.Matheus Almeida2014-05-121-0/+9
| | | | llvm-svn: 208592
* [mips] Move disassembler tests (Mips MSA test_i*, test_mi10) into correct ↵Matheus Almeida2014-05-124-0/+92
| | | | | | folder. llvm-svn: 208590
* [mips] Move disassembler tests (Mips MSA test_elm*) into correct folder.Matheus Almeida2014-05-125-0/+37
| | | | llvm-svn: 208589
* [mips] Move disassembler tests (Mips MSA test_lsa, test_dlsa) into correct ↵Matheus Almeida2014-05-122-0/+12
| | | | | | folder. llvm-svn: 208588
* [mips] Move disassembler test (Mips MSA test_ctrlregs) into correct folder.Matheus Almeida2014-05-121-0/+35
| | | | llvm-svn: 208587
* [mips] Move disassembler test (Mips MSA test_bit) into correct folder.Matheus Almeida2014-05-121-0/+50
| | | | llvm-svn: 208586
* [mips] Move disassembler tests (Mips MSA test_2r, test_2rf, test_3r, ↵Matheus Almeida2014-05-124-0/+379
| | | | | | | | test_3rf) into correct folder. llvm-svn: 208584
* This patch implements jalx instruction for Mips architecture.This ↵Vladimir Medic2014-03-034-0/+12
| | | | | | instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well. llvm-svn: 202706
* LL and SC decoder method fix.Zoran Jovanovic2014-01-152-0/+12
| | | | llvm-svn: 199316
* Added support for LWU microMIPS instruction.Zoran Jovanovic2014-01-152-0/+6
| | | | llvm-svn: 199315
* Support for microMIPS trap instruction with immediate operands.Zoran Jovanovic2013-11-132-0/+36
| | | | llvm-svn: 194569
* Support for microMIPS trap instructions 1.Zoran Jovanovic2013-11-072-0/+36
| | | | llvm-svn: 194205
* Support for microMIPS branch instructions.Zoran Jovanovic2013-11-042-0/+48
| | | | llvm-svn: 193992
* Support for microMIPS jump instructionsZoran Jovanovic2013-10-292-0/+24
| | | | llvm-svn: 193623
* Mips: Disassemble sign-extended 64 bit immediates properly.Benjamin Kramer2013-10-111-0/+3
| | | | | | This doesn't change the meaning of the output, but makes look right. PR17539. llvm-svn: 192483
* Fixed bug when generating Load Upper Immediate microMIPS instruction.Zoran Jovanovic2013-09-142-0/+6
| | | | llvm-svn: 190746
* Support for microMIPS DIV instructions.Zoran Jovanovic2013-09-142-0/+12
| | | | llvm-svn: 190745
* Support for misc microMIPS instructions.Zoran Jovanovic2013-09-142-0/+42
| | | | llvm-svn: 190744
* This patch adds support for microMIPS Multiply and Add/Sub instructions. ↵Vladimir Medic2013-09-062-0/+24
| | | | | | Test cases are included in patch. llvm-svn: 190154
* This patch adds support for microMIPS Move to/from HI/LO instructions. Test ↵Vladimir Medic2013-09-062-0/+24
| | | | | | cases are included in patch. llvm-svn: 190152
* This patch adds support for microMIPS Move Conditional instructions. Test ↵Vladimir Medic2013-09-062-0/+24
| | | | | | cases are included in patch. llvm-svn: 190148
* This patch adds support for microMIPS disassembler and disassembler make ↵Vladimir Medic2013-09-062-0/+298
| | | | | | check tests. llvm-svn: 190144
* [mips] Use ptr_rc to simplify definitions of base+index load/store instructions.Akira Hatanaka2013-08-285-0/+69
| | | | | | Also, fix predicates. llvm-svn: 189432
* [tests] Cleanup initialization of test suffixes.Daniel Dunbar2013-08-161-2/+0
| | | | | | | | | | | | | | | | | - Instead of setting the suffixes in a bunch of places, just set one master list in the top-level config. We now only modify the suffix list in a few suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py). - Aside from removing the need for a bunch of lit.local.cfg files, this enables 4 tests that were inadvertently being skipped (one in Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been XFAILED). - This commit also fixes a bunch of config files to use config.root instead of older copy-pasted code. llvm-svn: 188513
* [mips] Fix FP conditional move instructions to have explicit FP condition codeAkira Hatanaka2013-07-262-0/+36
| | | | | | register operands. llvm-svn: 187242
* [mips] Fix FP branch instructions to have explicit FP condition code registerAkira Hatanaka2013-07-264-0/+24
| | | | | | operands. llvm-svn: 187238
* [mips] Print instructions "beq", "bne" and "or" using assembler pseudoAkira Hatanaka2013-07-261-0/+6
| | | | | | | | | | instructions "beqz", "bnez" and "move", when possible. beq $2, $zero, $L1 => beqz $2, $L1 bne $2, $zero, $L1 => bnez $2, $L1 or $2, $3, $zero => move $2, $3 llvm-svn: 187229
* [mips] Increase the number of floating point control registers available to 32.Akira Hatanaka2013-07-014-16/+16
| | | | | | | Create a dedicated register class for floating point condition code registers and move FCC0 from register class CCR to the new register class. llvm-svn: 185373
* [Mips Disassembler] Have the DecodeCCRRegisterClass function use the getRegChad Rosier2013-06-264-16/+16
| | | | | | | function to lookup the proper tablegen'ed register enumeration. Previously, it was using the encoded value directly. llvm-svn: 185026
* [mips] DSP-ASE move from HI/LO register instructions.Akira Hatanaka2013-04-181-0/+13
| | | | llvm-svn: 179739
* Use object file specific section type for initial text sectionNico Rieck2013-04-148-8/+0
| | | | llvm-svn: 179494
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-172-0/+12
| | | | | | | | | | | | | but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic llvm-svn: 172685
* reverting 172579Jack Carter2013-01-162-12/+0
| | | | llvm-svn: 172594
* Akira,Jack Carter2013-01-162-0/+12
| | | | | | | | | | | | Hope you are feeling better. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic llvm-svn: 172579
* Remove DOS line endings.Jakub Staszak2012-11-144-316/+316
| | | | llvm-svn: 167968
* [mips] Fix disassembler test cases.Akira Hatanaka2012-11-024-24/+24
| | | | llvm-svn: 167326
* Fix check strings in test/MC/Disassembler/Mips/* and run FileCheck.Akira Hatanaka2012-07-128-760/+694
| | | | | | Patch by Vladimir Medic. llvm-svn: 160143
* Reapply r158846.Akira Hatanaka2012-07-094-160/+172
| | | | | | | Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
* revert r159851.Akira Hatanaka2012-07-064-172/+160
| | | | llvm-svn: 159854
* Reapply r158846.Akira Hatanaka2012-07-064-160/+172
| | | | | | Include file MipsGenRegisterInfo.inc. llvm-svn: 159851
* Revert r158846.Akira Hatanaka2012-06-204-172/+160
| | | | llvm-svn: 158855
* In MipsDisassembler.cpp, instead of defining register class tables, use the onesAkira Hatanaka2012-06-204-160/+172
| | | | | | | | | | | that are generated by TableGen and are already available in MipsGenRegisterInfo.inc. Suggested by Jakob Stoklund Olesen. Also, fix bug in function DecodeAFGR64RegisterClass. Patch by Vladimir Medic. llvm-svn: 158846
* Add lit.local.cfg to run the tests in test/MC/Disassembler/Mips.Akira Hatanaka2012-05-311-0/+6
| | | | llvm-svn: 157725
* Add disassembler to MIPS. Akira Hatanaka2012-04-178-0/+2042
| | | | | | Patch by Vladimir Medic. llvm-svn: 154935
* Revert r153924. Delete test/MC/Disassembler/Mips and ↵Akira Hatanaka2012-04-038-0/+0
| | | | | | lib/Target/Mips/Disassembler. llvm-svn: 153926
* Revert r153924. There were buildbot failures.Akira Hatanaka2012-04-038-2042/+0
| | | | llvm-svn: 153925
* MIPS disassembler support.Akira Hatanaka2012-04-038-0/+2042
Patch by Vladimir Medic. llvm-svn: 153924
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