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* [mips] Add backend support for Mips32r[35] and Mips64r[35].Daniel Sanders2015-02-1813-1/+1931
| | | | | | | | | | | | | | | | | Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
* [mips] Merge disassemblers into a single implementation.Daniel Sanders2015-02-114-0/+12
| | | | | | | | | | | | | | | | | | | | Summary: Currently we have Mips32 and Mips64 disassemblers and this causes the target triple to affect the disassembly despite all the relevant information being in the ELF header. These implementations do not need to be separate. This patch merges them together such that the appropriate tables are checked for the subtarget (e.g. Mips64 is checked when GP64 is enabled). Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7498 llvm-svn: 228825
* [mips][microMIPS] Implement movep instructionZoran Jovanovic2015-02-102-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D7465 llvm-svn: 228703
* [mips][microMIPS] Add disassembler tests for 16-bit instructions BREAK16 and ↵Jozef Kolek2015-02-102-0/+12
| | | | | | | | SDBBP16 Differential Revision: http://reviews.llvm.org/D7443 llvm-svn: 228687
* [mips][microMIPS] Fix disassembling of 16-bit microMIPS instructions LWM16 ↵Jozef Kolek2015-02-102-0/+12
| | | | | | | | and SWM16 Differential Revision: http://reviews.llvm.org/D7436 llvm-svn: 228683
* [Mips][Disassembler] When disassembler meets cache/pref instructions for r6 ↵Vladimir Medic2015-01-296-7/+8
| | | | | | it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions. llvm-svn: 227430
* [mips][microMIPS] Implement LWGP instructionJozef Kolek2015-01-282-0/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D6650 llvm-svn: 227325
* When disassembler meets compact jump instructions for r6 it crashes as the ↵Vladimir Medic2015-01-266-4/+11
| | | | | | access to operands array is out of range. This patch removes dedicated decoder method that wrongly handles decoding of these instructions. llvm-svn: 227084
* mips: Fix "XPASS" test results by removing 'not' commandsReid Kleckner2015-01-232-2/+2
| | | | | | | | | | | These tests are asserting and crashing for me, and 'not' sees that as a non-zero exit code instead of a signal code for obscure Windows reasons. This causes the test to pass, giving me an unclean 'ninja check'. The test is already XFAILd, so just run the test without 'not' and let lit handle the failure. llvm-svn: 226958
* [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction BJozef Kolek2015-01-212-0/+6
| | | | | | | | | | | | | | Implement microMIPS 16-bit unconditional branch instruction B. Implemented 16-bit microMIPS unconditional instruction has real name B16, and B is an alias which expands to either B16 or BEQ according to the rules: b 256 --> b16 256 # R_MICROMIPS_PC10_S1 b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1 b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1 Differential Revision: http://reviews.llvm.org/D3514 llvm-svn: 226657
* [mips][microMIPS] Implement ADDIUPC instructionJozef Kolek2015-01-212-0/+18
| | | | | | Differential Revision: http://reviews.llvm.org/D6582 llvm-svn: 226656
* [Mips][Disassembler]When disassembler meets load/store from coprocessor 2 ↵Vladimir Medic2015-01-216-8/+16
| | | | | | instructions for mips r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method that properly handles decoding of these instructions. llvm-svn: 226652
* Reverted revision 226577.Jozef Kolek2015-01-202-6/+0
| | | | llvm-svn: 226595
* [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction BJozef Kolek2015-01-202-0/+6
| | | | | | | | | | | | | | Implement microMIPS 16-bit unconditional branch instruction B. Implemented 16-bit microMIPS unconditional instruction has real name B16, and B is an alias which expands to either B16 or BEQ according to the rules: b 256 --> b16 256 # R_MICROMIPS_PC10_S1 b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1 b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1 Differential Revision: http://reviews.llvm.org/D3514 llvm-svn: 226577
* [mips] 'CHECK :' is not a valid check directive. Fixed.Daniel Sanders2015-01-185-301/+301
| | | | llvm-svn: 226409
* [mips] Make whitespace in disassembler tests more consistent. NFC.Daniel Sanders2015-01-1828-3854/+3854
| | | | | | | | | | The tests for the ISA's should now be approximately diffable. That is, the output of 'diff valid-mips1.txt valid-mips2.txt' should be emit the lines for instructions that were added/removed to/from MIPS-I by MIPS-II. This doesn't work perfectly at the moment due to ordering differences but it should be close. llvm-svn: 226408
* [mips] Make whitespace of disassembler tests more consistent by removing ↵Daniel Sanders2015-01-1815-1523/+0
| | | | | | blank lines. NFC. llvm-svn: 226407
* Add disassembler tests for mips64r6 platform. There are no functional changes.Vladimir Medic2015-01-153-0/+348
| | | | llvm-svn: 226166
* Add disassembler tests for mips32r6 platform. There are no functional changes.Vladimir Medic2015-01-153-0/+307
| | | | llvm-svn: 226165
* Add disassembler tests for mips64r2 platform. There are no functional changes.Vladimir Medic2015-01-153-0/+1008
| | | | llvm-svn: 226164
* Add disassembler tests for mips64 platform. There are no functional changes.Vladimir Medic2015-01-153-0/+936
| | | | llvm-svn: 226151
* Add disassembler tests for mips32r2 platform. There are no functional changes.Vladimir Medic2015-01-143-0/+757
| | | | llvm-svn: 225980
* Add disassembler tests for mips32r2 platform. There are no functional changes.Vladimir Medic2015-01-143-0/+618
| | | | llvm-svn: 225967
* [mips][microMIPS] Implement BEQZ16 and BNEZ16 instructionsJozef Kolek2015-01-122-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D5271 llvm-svn: 225627
* [mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructionsJozef Kolek2014-12-232-0/+30
| | | | | | Differential Revision: http://reviews.llvm.org/D5204 llvm-svn: 224785
* [mips][microMIPS] Implement LWSP and SWSP instructionsJozef Kolek2014-12-232-0/+24
| | | | | | Differential Revision: http://reviews.llvm.org/D6416 llvm-svn: 224771
* [mips][microMIPS] Implement SWP and LWP instructionsZoran Jovanovic2014-12-162-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D5667 llvm-svn: 224338
* Add disassembler tests for mips4 platform. There are no functional changes.Vladimir Medic2014-12-163-0/+500
| | | | llvm-svn: 224335
* Move mips1 tests to test/MC/Disassembler/Mips/mips1Reid Kleckner2014-12-153-0/+237
| | | | | | | This matches the pattern of the mips2 and 3 tests, as well as our normal conventions. llvm-svn: 224254
* Add disassembler tests for mips3 platform. There are no functional changes.Vladimir Medic2014-12-152-0/+418
| | | | llvm-svn: 224253
* Add disassembler tests for mips2 platform. There are no functional changes.Vladimir Medic2014-12-152-0/+318
| | | | llvm-svn: 224252
* The andi16, addiusp and jraddiusp micromips instructions were missing ↵Vladimir Medic2014-12-012-0/+42
| | | | | | dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests. llvm-svn: 223006
* [mips][microMIPS] Implement NOP aliasesJozef Kolek2014-11-292-0/+12
| | | | | | | | | This patch implements microMIPS 16-bit (MOVE16 $0, $0) and 32-bit (SLL $0, $0, 0) NOP aliases. http://reviews.llvm.org/D6440 llvm-svn: 222953
* [mips] Add synci instruction.Daniel Sanders2014-11-272-0/+6
| | | | | | | | | | | | | | Patch by Amaury Pouly Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6421 llvm-svn: 222899
* [mips][microMIPS] Implement disassembler support for 16-bit instructions ↵Jozef Kolek2014-11-272-0/+36
| | | | | | | | LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5 Differential Revision: http://reviews.llvm.org/D6419 llvm-svn: 222887
* [mips][microMIPS] Implement disassembler support for 16-bit instructions ↵Jozef Kolek2014-11-262-0/+48
| | | | | | | | LBU16, LHU16, LW16, SB16, SH16 and SW16 Differential Revision: http://reviews.llvm.org/D6405 llvm-svn: 222847
* [mips][microMIPS] Implement disassembler support for 16-bit instructionsJozef Kolek2014-11-242-0/+90
| | | | | | | | | | | With the help of new method readInstruction16() two bytes are read and decodeInstruction() is called with DecoderTableMicroMips16, if this fails four bytes are read and decodeInstruction() is called with DecoderTableMicroMips32. Differential Revision: http://reviews.llvm.org/D6149 llvm-svn: 222648
* [mips][micromips] Implement SWM32 and LWM32 instructionsZoran Jovanovic2014-11-192-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D5519 llvm-svn: 222367
* [mips][microMIPS] Add disassembler tests for new microMIPS 32-bitJozef Kolek2014-11-192-0/+42
| | | | | | | | instructions: LWXS, BGEZALS, BLTZALS, BEQZC, BNEZC, JALS and JALRS. http://reviews.llvm.org/D5413 llvm-svn: 222349
* [mips] Fix disassembly of [ls][wd]c[23], cache, and pref ↵Daniel Sanders2014-10-013-0/+32
| | | | | | | | Fixes PR21015, and PR20993. Patch by Jun Koi llvm-svn: 218745
* [mips][mips64r6] Correct cond names in the cmp.cond.[ds] instructionsDaniel Sanders2014-07-092-40/+40
| | | | | | | | | | Summary: It seems we accidentally read the wrong column of the table MIPS64r6 spec and used the names for c.cond.fmt instead of cmp.cond.fmt. Differential Revision: http://reviews.llvm.org/D4387 llvm-svn: 212607
* [mips][mips64r6] Correct the encoding of dmuh, dmuhu, dmul, and dmulu.Daniel Sanders2014-07-041-4/+4
| | | | | | | | We have detected a documentation bug in the encoding tables of the released MIPS64r6 specification that has resulted in the wrong encodings being used for these instructions in LLVM. This commit corrects them. llvm-svn: 212330
* [mips][mips64r6] Add BLTC and BLTUC instructionsZoran Jovanovic2014-06-182-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D3923 llvm-svn: 211167
* [mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6Daniel Sanders2014-06-162-0/+6
| | | | | | | | | | | | | | | | | Summary: There is no change to the restrictions, just the result register is stored once in the encoding rather than twice. The rt field is zero in MIPS32r6/MIPS64r6. Depends on D4119 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4120 llvm-svn: 211019
* [mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6.Daniel Sanders2014-06-162-0/+6
| | | | | | | | | | | | | | | | | | | | | Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018
* [mips][mips64r6] Add bgec and bgeuc instructionsZoran Jovanovic2014-06-122-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D4017 llvm-svn: 210770
* [mips] Implement jr.hb and jalr.hb (Jump Register and Jump and Link Register ↵Matheus Almeida2014-06-112-0/+6
| | | | | | | | | | | | | | with Hazard Barrier). Summary: These instructions are available in ISAs >= mips32/mips64. For mips32r6/mips64r6, jr.hb has a new encoding format. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4019 llvm-svn: 210654
* Reduce verbiage of lit.local.cfg filesAlp Toker2014-06-091-2/+1
| | | | | | We can just split targets_to_build in one place and make it immutable. llvm-svn: 210496
* [mips][mips64r6] Add LDPC instructionZoran Jovanovic2014-06-091-0/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D3822 llvm-svn: 210460
* [mips][mips64r6] Add b[on]vcDaniel Sanders2014-05-222-0/+245
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
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