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* STRT and STRBT was incorrectly tagged as IndexModeNone during the ↵Johnny Chen2011-03-241-0/+3
| | | | | | | | refactorings (r119821). We now tag them as IndexModePost. llvm-svn: 128189
* The r128103 fix to cope with the removal of addressing modes from the MC ↵Johnny Chen2011-03-241-0/+3
| | | | | | | | | | instructions were incomplete. The assert stmt needs to be updated and the operand index incrment is wrong. Fix the bad logic and add some sanity checking to detect bad instruction encoding; and add a test case. llvm-svn: 128186
* Add disassembly test cases for:Johnny Chen2011-03-222-0/+6
| | | | | | A8.6.292 VCMPE llvm-svn: 128120
* LDRT and LDRBT was incorrectly tagged as IndexModeNone during the ↵Johnny Chen2011-03-221-0/+3
| | | | | | | | | | refactorings (r119821). We now tag them as IndexModePost. This fixed http://llvm.org/bugs/show_bug.cgi?id=9530. llvm-svn: 128113
* Add one more test case for VFP Load/Store Multiple (vpop).Johnny Chen2011-03-221-0/+3
| | | | llvm-svn: 128106
* A8.6.399 VSTM:Johnny Chen2011-03-221-0/+3
| | | | | | | | | | | VFP Load/Store Multiple Instructions used to embed the IA/DB addressing mode within the MC instruction; that has been changed so that now, for example, VSTMDDB_UPD and VSTMDIA_UPD are two instructions. Update the ARMDisassemblerCore.cpp's DisassembleVFPLdStMulFrm() to reflect the change. Also add a test case. llvm-svn: 128103
* Fixed an assert by the ARM disassembler for LDRD_PRE/POST.Johnny Chen2011-03-191-0/+3
| | | | | | | | The relevant instruction table entries were changed sometime ago to no longer take <Rt2> as an operand. Modify ARMDisassemblerCore.cpp to accomodate the change and add a test case. llvm-svn: 127935
* The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset.Johnny Chen2011-03-181-3/+3
| | | | | | Remove the offending logic and update the test cases. llvm-svn: 127843
* It used to be that t_addrmode_s4 was used for both:Johnny Chen2011-03-171-0/+9
| | | | | | | | | | | o A8.6.195 STR (register) -- Encoding T1 o A8.6.193 STR (immediate, Thumb) -- Encoding T1 It has been changed so that now they use different addressing modes and thus different MC representation (Operand Infos). Modify the disassembler to reflect the change, and add relevant tests. llvm-svn: 127833
* There were two issues fixed:Johnny Chen2011-03-151-1/+7
| | | | | | | | | | | | | | | | 1. The ARM Darwin *r9 call instructions were pseudo-ized recently. Modify the ARMDisassemblerCore.cpp file to accomodate the change. 2. The disassembler was unnecessarily adding 8 to the sign-extended imm24: imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate) // Encoding A1 It has no business doing such. Removed the offending logic. Add test cases to arm-tests.txt. llvm-svn: 127707
* Fixed an ARM disassembler bug where it does not handle STRi12 correctly ↵Johnny Chen2011-03-151-0/+12
| | | | | | | | | | because an extra register operand was erroneously added. Remove an incorrect assert which triggers the bug. rdar://problem/9131529 llvm-svn: 127642
* LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT.Johnny Chen2011-03-091-0/+3
| | | | | | | | | The insufficient encoding information of the combined instruction confuses the decoder wrt UQADD16. Add extra logic to recover from that. Fixed an assert reported by Sean Callanan llvm-svn: 127354
* TableGen should not ignore BX instructions for the ARM disassembler. pr9368.Bob Wilson2011-03-031-0/+3
| | | | llvm-svn: 126931
* pr9367: Add missing predicated BLX instructions.Bob Wilson2011-03-031-0/+3
| | | | | | Patch by Jyun-Yan You, with some minor adjustments and a testcase from me. llvm-svn: 126915
* Fixes an assertion failure while disassembling ARM rsbs reg/reg form.Kevin Enderby2011-03-021-0/+3
| | | | | | Patch by Ted Kremenek! llvm-svn: 126895
* Fix the arm's disassembler for blx that was building an MCInst without theKevin Enderby2011-02-281-0/+3
| | | | | | needed two predicate operands before the imm operand. llvm-svn: 126662
* Add assembly parsing support for "msr" and also fix its encoding. Also addBruno Cardoso Lopes2011-02-182-0/+6
| | | | | | testcases for the disassembler to make sure it still works for "msr". llvm-svn: 125948
* Fix encoding and add parsing support for the arm/thumb CPS instruction:Bruno Cardoso Lopes2011-02-142-0/+21
| | | | | | | | | | | | - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. llvm-svn: 125489
* Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 ↵Owen Anderson2011-02-081-1/+1
| | | | | | (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. llvm-svn: 125127
* PR9030: Fix disassembly of ARM "mov pc, lr" instruction.Bob Wilson2011-01-281-0/+3
| | | | | | Patch by Jyun-Yan You. llvm-svn: 124492
* As far as I can tell, unified syntax uses c0-c15 instead of cr0-cr15 for mcr ↵Owen Anderson2011-01-131-1/+1
| | | | | | and friends. llvm-svn: 123407
* Second attempt at converting Thumb2's LDRpci, including updating the ↵Owen Anderson2010-12-071-1/+1
| | | | | | gazillion places that need to know about it. llvm-svn: 121082
* When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's theJim Grosbach2010-12-031-2/+2
| | | | | | 32-bit wide version by adding the .w suffix. llvm-svn: 120838
* Add correct encodings for STRD and LDRD, including fixup support. ↵Owen Anderson2010-12-011-1/+1
| | | | | | Additionally, update these to unified syntax. llvm-svn: 120589
* Segregate tests by target.Dale Johannesen2010-11-144-0/+289
llvm-svn: 119050
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