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* Push GPRnopc through a large number of instruction definitions to tighten ↵Owen Anderson2011-08-106-14/+8
| | | | | | operand decoding. llvm-svn: 137189
* Tighten operand checking of register-shifted-register operands.Owen Anderson2011-08-092-4/+2
| | | | llvm-svn: 137180
* Tighten operand checking on memory barrier instructions.Owen Anderson2011-08-093-9/+6
| | | | llvm-svn: 137176
* Tighten operand checking on CPS instructions.Owen Anderson2011-08-092-2/+0
| | | | llvm-svn: 137172
* Create a new register class for the set of all GPRs except the PC. Use it ↵Owen Anderson2011-08-091-1/+0
| | | | | | to tighten our decoding of BFI. llvm-svn: 137168
* ARM Disassembler: sign extend branch immediates.Benjamin Kramer2011-08-091-0/+3
| | | | | | Not sure about BLXi, but this is what the old disassembler did. llvm-svn: 137156
* Tighten Thumb1 branch predicate decoding.Owen Anderson2011-08-091-1/+0
| | | | llvm-svn: 137146
* Replace the existing ARM disassembler with a new one based on the ↵Owen Anderson2011-08-0946-25/+60
| | | | | | | | | | FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
* ARM refactoring assembly parsing of memory address operands.Jim Grosbach2011-08-031-2/+5
| | | | | | | | | | | | | | | | | | | | | | Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
* ARM SRS instruction parsing, diassembly and encoding support.Jim Grosbach2011-07-291-0/+6
| | | | | | | | Fix the instruction encoding for operands. Refactor mode to use explicit instruction definitions per FIXME to be more consistent with loads/stores. Fix disassembler accordingly. Add tests. llvm-svn: 136509
* Tweak ARM assembly parsing and printing of MSR instruction.Jim Grosbach2011-07-192-3/+3
| | | | | | | | The system register spec should be case insensitive. The preferred form for output with mask values of 4, 8, and 12 references APSR rather than CPSR. Update and tidy up tests accordingly. llvm-svn: 135532
* Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues ↵Owen Anderson2011-07-151-1/+1
| | | | | | to simplify the path towards an auto-generated disassembler. llvm-svn: 135290
* Simplify printing of ARM shifted immediates.Jim Grosbach2011-07-111-4/+4
| | | | | | | | | Print shifted immediate values directly rather than as a payload+shifter value pair. This makes for more readable output assembly code, simplifies the instruction printer, and is consistent with how Thumb immediates are displayed. llvm-svn: 134902
* Fix Bug 9386 - ARM disassembler failed to disassemble conditional bxJohnny Chen2011-05-221-0/+3
| | | | | | | Modified the patch to .td file supplied by Jyun-Yan You. Add a test case and modified ARMDisassemblerCore.cpp a little bit. llvm-svn: 131859
* Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' ↵Johnny Chen2011-05-181-0/+3
| | | | | | immediate operand. llvm-svn: 131565
* Add tests for A8.6.110 NOP.Johnny Chen2011-04-272-0/+9
| | | | llvm-svn: 130345
* Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) ↵Johnny Chen2011-04-222-3/+6
| | | | | | | | | | should print out ldr, not ldr.n. rdar://problem/9267772 llvm-svn: 130008
* Thumb2 BFC was insufficiently encoded.Johnny Chen2011-04-151-0/+3
| | | | | | rdar://problem/9292717 llvm-svn: 129619
* A8.6.315 VLD3 (single 3-element structure to all lanes)Johnny Chen2011-04-151-0/+11
| | | | | | | | The a bit must be encoded as 0. rdar://problem/9292625 llvm-svn: 129618
* The ARM disassembler did not handle the alignment correctly for VLD*DUP* ↵Johnny Chen2011-04-152-0/+16
| | | | | | | | instructions (single element or n-element structure to all lanes). llvm-svn: 129550
* Add sanity checkings for Thumb2 Load/Store Register Exclusive family of ↵Johnny Chen2011-04-144-0/+33
| | | | | | operations. llvm-svn: 129531
* Thumb disassembler did not handle tBRIND (indirect branch) properly.Johnny Chen2011-04-131-0/+3
| | | | | | rdar://problem/9280370 llvm-svn: 129480
* Check for unallocated instruction encodings when disassembling Thumb Branch ↵Johnny Chen2011-04-132-2/+13
| | | | | | | | instructions (tBcc and t2Bcc). rdar://problem/9280470 llvm-svn: 129471
* The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.Johnny Chen2011-04-131-0/+10
| | | | | | rdar://problem/9279440 llvm-svn: 129469
* Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings ↵Johnny Chen2011-04-132-0/+20
| | | | | | | | as such. rdar://problem/9276651 llvm-svn: 129462
* Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was ↵Johnny Chen2011-04-131-0/+3
| | | | | | | | not properly handled. rdar://problem/9276427 llvm-svn: 129456
* Add sanity check for Ld/St Dual forms of Thumb2 instructions.Johnny Chen2011-04-122-0/+23
| | | | | | rdar://problem/9273947 llvm-svn: 129411
* The Thumb2 RFE instructions need to have their second halfword fully specified.Johnny Chen2011-04-121-0/+3
| | | | | | | | | | In addition, the base register is not rGPR, but GPR with th exception that: if n == 15 then UNPREDICTABLE rdar://problem/9273836 llvm-svn: 129391
* Add bad register checks for Thumb2 Ld/St instructions.Johnny Chen2011-04-121-0/+10
| | | | | | rdar://problem/9269047 llvm-svn: 129387
* The Thumb2 Ld, St, and Preload instructions with the i12 forms should have ↵Johnny Chen2011-04-121-1/+13
| | | | | | | | | | its Inst{23} be specified as '1' (add = TRUE). Also add a utility function for Thumb2. llvm-svn: 129377
* Print out a debug message when the reglist fails the sanity check for Thumb ↵Johnny Chen2011-04-121-0/+10
| | | | | | Ld/St Multiple. llvm-svn: 129365
* Add one test case (svc).Johnny Chen2011-04-121-0/+3
| | | | llvm-svn: 129327
* A8.6.16 BJohnny Chen2011-04-121-0/+10
| | | | | | | | | Encoding T1 (tBcc) if cond == '1110' then UNDEFINED; rdar://problem/9268681 llvm-svn: 129325
* Thumb disassembler was erroneously rejecting "blx sp" instruction.Johnny Chen2011-04-111-0/+9
| | | | | | rdar://problem/9267838 llvm-svn: 129320
* Fix the bug where the immediate shift amount for Thumb logical shift ↵Johnny Chen2011-04-111-0/+6
| | | | | | | | instructions are incorrectly disassembled. rdar://problem/9266265 llvm-svn: 129298
* Check invalid register encodings for LdFrm/StFrm ARM instructions and flag ↵Johnny Chen2011-04-114-0/+34
| | | | | | | | them as invalid instructions. llvm-svn: 129286
* Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.Johnny Chen2011-04-081-0/+3
| | | | | | | PR9650 rdar://problem/9257565 llvm-svn: 129147
* Sanity check the option operand for DMB/DSB.Johnny Chen2011-04-083-0/+38
| | | | | | | PR9648 rdar://problem/9257634 llvm-svn: 129146
* MOVi16 and MOVTi16 does not allow pc as the dest register, while MOVi allows it.Johnny Chen2011-04-082-0/+16
| | | | | | Add tests for that. llvm-svn: 129137
* Add sanity checking for bad register specifier(s) for the DPFrm instructions.Johnny Chen2011-04-084-0/+50
| | | | | | Add more test cases to exercise the logical branches related to the above change. llvm-svn: 129117
* Add a VEXT test.Johnny Chen2011-04-071-0/+3
| | | | llvm-svn: 129111
* Add sanity checking for invalid register encodings for signed/unsigned ↵Johnny Chen2011-04-072-0/+17
| | | | | | | | extend instructions. Add some test cases. llvm-svn: 129098
* Add sanity checking for invalid register encodings for saturating instructions.Johnny Chen2011-04-071-0/+11
| | | | llvm-svn: 129096
* Add some more comments about checkings of invalid register numbers.Johnny Chen2011-04-072-0/+14
| | | | | | And two test cases. llvm-svn: 129090
* Sanity check MSRi for invalid mask values and reject it as invalid.Johnny Chen2011-04-071-0/+12
| | | | | | rdar://problem/9246844 llvm-svn: 129050
* The ARM disassembler was not recognizing USADA8 instruction. Need to add ↵Johnny Chen2011-04-071-0/+3
| | | | | | | | | | checking for register values for USAD8 and USADA8. rdar://problem/9247060 llvm-svn: 129047
* Should also check SMLAD for invalid register values.Johnny Chen2011-04-071-0/+11
| | | | | | rdar://problem/9246650 llvm-svn: 129042
* A8.6.393Johnny Chen2011-04-061-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | The ARM disassembler should reject invalid (type, align) encodings as invalid instructions. So, instead of: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- vst2.32 {d0, d2}, [r3, :256], r3 we now have: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- mc-input.txt:1:1: warning: invalid instruction encoding 0xb3 0x9 0x3 0xf4 ^ llvm-svn: 129033
* A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"Johnny Chen2011-04-063-0/+16
| | | | | | | | | | Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits specified, if coproc == 10 or 11, we should reject the insn as invalid. rdar://problem/9239922 rdar://problem/9239596 llvm-svn: 129027
* Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.Johnny Chen2011-04-061-0/+3
| | | | | | | | | Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000, in class NVLaneOp. rdar://problem/9240648 llvm-svn: 129015
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