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* [ARMv8] Add some disassembly tests for Thumb sevl/sevl.wJoey Gouly2013-10-071-0/+5
| | | | llvm-svn: 192106
* [ARM] Introduce the 'sevl' instruction in ARMv8.Joey Gouly2013-10-014-11/+7
| | | | | | | This also removes the restriction on the immediate field of the 'hint' instruction. llvm-svn: 191744
* Fix spelling intruction -> instruction.Robert Wilhelm2013-09-281-2/+2
| | | | llvm-svn: 191610
* [ARMv8] Add support for the v8 cryptography extensions.Amara Emerson2013-09-192-0/+70
| | | | llvm-svn: 190996
* 'svn add' the test cases.Joey Gouly2013-09-182-0/+30
| | | | llvm-svn: 190929
* Fix tests for hasFPARMv8 name change (r190692)Amaury de la Vieuville2013-09-132-2/+2
| | | | | | Patch by Bradley Smith llvm-svn: 190694
* [ARMv8] Add some missing tests for DSB/DMB.Joey Gouly2013-09-052-2/+21
| | | | llvm-svn: 190060
* Add AArch32 DCPS{1,2,3} and HLT instructions.Richard Barton2013-09-052-0/+29
| | | | | | | | | | | | | | | | | These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. llvm-svn: 190053
* [ARMv8] Add MC support for the new load/store acquire/release instructions.Joey Gouly2013-08-272-0/+65
| | | | llvm-svn: 189388
* [tests] Cleanup initialization of test suffixes.Daniel Dunbar2013-08-161-2/+0
| | | | | | | | | | | | | | | | | - Instead of setting the suffixes in a bunch of places, just set one master list in the top-level config. We now only modify the suffix list in a few suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py). - Aside from removing the need for a bunch of lit.local.cfg files, this enables 4 tests that were inadvertently being skipped (one in Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been XFAILED). - This commit also fixes a bunch of config files to use config.root instead of older copy-pasted code. llvm-svn: 188513
* This fixes the Thumb2 CPS assembly syntax.Mihai Popa2013-08-091-1/+1
| | | | | | | | | | | | | | In Thumb1, only one variant is supported: CPS{effect} {flags} Thumb2 supports three: CPS{effect}.W {flags} CPS{effect} {flags} {mode} CPS {mode} Canonically, .W should be used only when ambiguity is present between encodings of different width. The wide suffix is still accepted for the latter two forms via aliases. llvm-svn: 188071
* Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.Kevin Enderby2013-07-311-0/+2
| | | | | | | | | | | While the .td entry is nice and all, it takes a pretty gross hack in ARMAsmParser::ParseInstruction() because of handling of other "subs" instructions to get it to match. Ran it by Jim Grosbach and he said it was about what he expected to make this work given the existing code. rdar://14214063 llvm-svn: 187530
* Add not so that these tests pass with pipefail enabled.Rafael Espindola2013-07-233-3/+3
| | | | llvm-svn: 186939
* [ARMv8] Implement the NEON instructions VRINT{N, X, A, Z, M, P}.Joey Gouly2013-07-192-0/+50
| | | | llvm-svn: 186688
* ARM: delete two tests now integrated into the larger filesTim Northover2013-07-192-19/+0
| | | | | | | | Somehow forgot to git rm these two files. I believe I left the remaining invalid* tests intentionally, though whether my reasons were sound is a different matter. llvm-svn: 186663
* ARM: remove invalid invalid testsTim Northover2013-07-192-32/+0
| | | | | | | | | | | The tests were checking for barriers which the ARM ARM says they must execute as a full system DMB/DSB, rather than that they're UNDEFINED and LLVM does in fact represent them. The tests happened to be passing because they were using a non-versioned ARM triple which didn't have *any* DMB/DSB instructions. llvm-svn: 186662
* Improve llvm-mc disassembler mode and refactor ARM tests to use itTim Northover2013-07-1963-611/+972
| | | | | | | | | | | | | | | | | | This allows "llvm-mc -disassemble" to accept two new features: + Using comma as a byte separator + Grouping bytes with '[' and ']' pairs. The behaviour outside a [...] group is unchanged. But within the group once llvm-mc encounters a true error, it stops rather than trying to resynchronise the stream at the next byte. This is more useful for disassembly tests, where we have an almost-instruction in mind and don't care what the misaligned interpretation would be. Particularly if it means llvm-mc won't actually see the next intended almost-instruction. As a side effect, this means llvm-mc can disassemble its own -show-encoding output if copy-pasted. llvm-svn: 186661
* [ARMv8] Add NEON instructions VCVT{A, N, P, M}.Joey Gouly2013-07-182-0/+72
| | | | llvm-svn: 186574
* Add Thumb tests for the ARMv8 FP instructions that I recently added.Joey Gouly2013-07-181-0/+163
| | | | | | Also, fix the namespace for two instructions that I missed previously. llvm-svn: 186572
* Add the tests that I forgot to 'svn add' with my previous commit (r186504).Joey Gouly2013-07-172-0/+20
| | | | llvm-svn: 186506
* Add MC assembly/disassembly support for VRINT{A, N, P, M} to V8FP.Joey Gouly2013-07-091-0/+24
| | | | llvm-svn: 185929
* Add MC assembly/disassembly support for VRINT{Z, X, R} to V8FP.Joey Gouly2013-07-091-0/+19
| | | | llvm-svn: 185926
* Add MC assembly/disassembly support for VCVT{A, N, P, M} to V8FP.Joey Gouly2013-07-091-0/+49
| | | | llvm-svn: 185922
* Add MC support for the v8fp instructions: vmaxnm and vminnm.Joey Gouly2013-07-061-0/+13
| | | | llvm-svn: 185767
* Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} ↵Joey Gouly2013-07-041-0/+25
| | | | | | | | | instructions. This adds a new decoder table/namespace 'VFPV8', as these instructions have their top 4 bits as 0b1111, while other Thumb instructions have 0b1110. llvm-svn: 185642
* Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision.Joey Gouly2013-07-042-0/+35
| | | | llvm-svn: 185620
* This corrects the implementation of Thumb ADR instruction. There are three ↵Mihai Popa2013-07-031-1/+5
| | | | | | | | | | issues: 1. it should accept only 4-byte aligned addresses 2. the maximum offset should be 1020 3. it should be encoded with the offset scaled by two bits llvm-svn: 185528
* ARM: operands should be explicit when disassembledAmaury de la Vieuville2013-06-261-0/+4
| | | | llvm-svn: 184943
* ARM: check predicate bits for thumb instructionsAmaury de la Vieuville2013-06-242-0/+18
| | | | | | | When encoded to thumb, VFP instruction and VMOV/VDUP between scalar and core registers, must have their predicate bit to 0b1110. llvm-svn: 184707
* ARM: rGPR is meant to be unpredictable, not undefinedAmaury de la Vieuville2013-06-242-3/+2
| | | | llvm-svn: 184706
* ARM: fix thumb1 nop decodingAmaury de la Vieuville2013-06-241-8/+2
| | | | | | | In thumb1, NOP is a pseudo-instruction equivalent to mov r8, r8. However the disassembler should not use this alias. llvm-svn: 184703
* ARM: fix IT decodingAmaury de la Vieuville2013-06-241-2/+6
| | | | | | mask == 0 -> UNPRED llvm-svn: 184702
* ARM: enable decoding of pc-relative PLD/PLIAmaury de la Vieuville2013-06-242-0/+32
| | | | llvm-svn: 184701
* This reverts r155000.Joey Gouly2013-06-202-4/+4
| | | | | | | | | The cdp2 instruction should have the same restrictions as cdp on the co-processor registers. VFP instructions on v8/AArch32 share the same encoding space as cdp2. llvm-svn: 184445
* ARM: add operands pre-writeback variants when neededAmaury de la Vieuville2013-06-181-0/+16
| | | | llvm-svn: 184181
* ARM: fix thumb literal loads decodingAmaury de la Vieuville2013-06-181-2/+55
| | | | | | | | This fixes two previous issues: - Negative offsets were not correctly disassembled - The decoded opcodes were not the right one llvm-svn: 184180
* ARM: thumb stores cannot use PC as dest registerAmaury de la Vieuville2013-06-181-0/+37
| | | | llvm-svn: 184179
* ARM: fix thumb coprocessor instruction with pre-writeback disassemblyAmaury de la Vieuville2013-06-141-0/+3
| | | | | | | was stc2 p0, c0, [r0]! instead of stc2 p0, c0, [r0,#0]! llvm-svn: 183975
* ARM: fix B decodingAmaury de la Vieuville2013-06-131-0/+2
| | | | llvm-svn: 183914
* This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These ↵Mihai Popa2013-06-111-2/+10
| | | | | | are optional registers that may be supported some ARM implementations to aid with resolution of floating point exceptions. The manual pages for vmsr and vmrs do not detail their use. Encodings and other information can be found in ARM Architecture Reference Manual section F, chapter 6, paragraph 3. llvm-svn: 183733
* ARM: Enforce decoding rules for VLDn instructionsAmaury de la Vieuville2013-06-113-38/+62
| | | | llvm-svn: 183731
* ARM: Fix STREX/LDREX reecodingAmaury de la Vieuville2013-06-112-0/+28
| | | | | | The decoded MCInst wasn't reencoded as the same instruction llvm-svn: 183729
* ARM: ISB cannot be passed the same options as DMBAmaury de la Vieuville2013-06-102-0/+4
| | | | | | ISB should only accepts full system sync, other options are reserved llvm-svn: 183656
* ARM: fix VMOVvnf32 decoding when ambiguous with VCVTAmaury de la Vieuville2013-06-081-0/+7
| | | | | | Enforce Table A7-15 (op=1, cmode=0b111) -> UNDEF llvm-svn: 183612
* ARM: enforce SRS decoding constraintsAmaury de la Vieuville2013-06-081-3/+7
| | | | llvm-svn: 183611
* ARM: fix CPS decoding when ambiguous with QADDAmaury de la Vieuville2013-06-082-0/+13
| | | | | | | | | Handle the case when the disassembler table can't tell the difference between some encodings of QADD and CPS. Add some necessary safe guards in CPS decoding as well. llvm-svn: 183610
* ARM: fix VCVT decodingAmaury de la Vieuville2013-06-081-0/+8
| | | | | | UNPRED was reported instead of UNDEF llvm-svn: 183608
* This is a simple patch that changes RRX and RRXS to accept all registers as ↵Mihai Popa2013-06-051-0/+23
| | | | | | | | operands. According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp. llvm-svn: 183307
* ARM: add fstmx and fldmx instructions for assemblyTim Northover2013-05-312-0/+22
| | | | | | | | | These instructions are deprecated oddities, but we still need to be able to disassemble (and reassemble) them if and when they're encountered. Patch by Amaury de la Vieuville. llvm-svn: 183011
* ARM: fix VEXT encoding corner caseTim Northover2013-05-311-0/+5
| | | | | | | | | | The disassembly of VEXT instructions was too lax in the bits checked. This fixes the case where the instruction affects Q-registers but a misaligned lane was specified (should be UNDEFINED). Patch by Amaury de la Vieuville llvm-svn: 183003
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