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* Add AVX version of CLMUL instructionsBruno Cardoso Lopes2010-07-232-0/+84
| | | | llvm-svn: 109248
* Add complete assembler support for FMA3 instructions, with descriptions and ↵Bruno Cardoso Lopes2010-07-232-0/+1348
| | | | | | encodings taken from the AVX manual llvm-svn: 109204
* Add remaining AVX instructions (most of them dealing with GR64 destinations. ↵Bruno Cardoso Lopes2010-07-221-0/+32
| | | | | | This complete the assembler support for the general AVX ISA. But we still miss instructions from FMA3 and CLMUL specific feature flags, which are now the next step llvm-svn: 109168
* Add more 256-bit forms for a bunch of regular AVX instructionsBruno Cardoso Lopes2010-07-212-0/+260
| | | | | | | Add 64-bit (GR64) versions of some instructions (which are not described in their SSE forms, but are described in AVX) llvm-svn: 109063
* Add missing AVX convert instructions. Those instructions are not described ↵Bruno Cardoso Lopes2010-07-212-0/+72
| | | | | | in their SSE forms (although they exist), but add the AVX forms anyway, so the assembler can benefit from it llvm-svn: 109039
* Add AVX only vzeroall and vzeroupper instructionsBruno Cardoso Lopes2010-07-211-0/+8
| | | | llvm-svn: 109002
* Add new AVX vpermilps, vpermilpd and vperm2f128 instructionsBruno Cardoso Lopes2010-07-212-0/+144
| | | | llvm-svn: 108984
* Add new AVX vmaskmov instructions, and also fix the VEX encoding bits to ↵Bruno Cardoso Lopes2010-07-212-0/+64
| | | | | | support it llvm-svn: 108983
* Add new AVX vextractf128 instructionsBruno Cardoso Lopes2010-07-202-0/+16
| | | | llvm-svn: 108964
* Include some tests for the recently committed ELF section directiveMatt Fleming2010-07-208-0/+48
| | | | | | handlers. llvm-svn: 108938
* Add new AVX instruction vinsertf128Bruno Cardoso Lopes2010-07-202-0/+16
| | | | llvm-svn: 108892
* x86_32 tests for vbroadcastBruno Cardoso Lopes2010-07-201-0/+16
| | | | llvm-svn: 108789
* Add AVX vbroadcast new instructionBruno Cardoso Lopes2010-07-201-0/+16
| | | | llvm-svn: 108788
* Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions!Bruno Cardoso Lopes2010-07-192-0/+144
| | | | llvm-svn: 108769
* X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the sameDaniel Dunbar2010-07-192-0/+6
| | | | | | | | instruction, we only want to allow the one for the current subtarget. - This also fixes suffix matching for jmp instructions, because it eliminates the ambiguity between 'jmpl' and 'jmpq'. llvm-svn: 108746
* X86-64: Mark WINCALL and more tail call instructions as code gen only.Daniel Dunbar2010-07-191-1/+1
| | | | llvm-svn: 108685
* MC/X86: We now match instructions like "incl %eax" correctly for the arch we areDaniel Dunbar2010-07-191-3/+3
| | | | | | assembling; remove crufty custom cleanup code. llvm-svn: 108681
* tests: Force another triple.Daniel Dunbar2010-07-191-1/+1
| | | | llvm-svn: 108666
* tests: Force triples.Daniel Dunbar2010-07-182-2/+2
| | | | llvm-svn: 108658
* MC/AsmParser: Fix .abort and .secure_log_unique to accept arbitrary tokenDaniel Dunbar2010-07-181-3/+3
| | | | | | sequences, not just strings. llvm-svn: 108655
* MC/AsmParser: Add macro argument substitution support.Daniel Dunbar2010-07-182-0/+45
| | | | llvm-svn: 108654
* MC/AsmParser: Add basic support for macro instantiation.Daniel Dunbar2010-07-181-1/+1
| | | | llvm-svn: 108653
* MC/AsmParser: Add basic parsing support for .macro definitions.Daniel Dunbar2010-07-181-4/+19
| | | | llvm-svn: 108652
* MC/AsmParser: Add .macros_{off,on} support, not that makes sense since we don'tDaniel Dunbar2010-07-181-0/+8
| | | | | | support macros. llvm-svn: 108649
* Test for ELF .size directive.Eli Friedman2010-07-171-0/+8
| | | | llvm-svn: 108607
* Add AVX 256-bit compare instructions and a bunch of testcasesBruno Cardoso Lopes2010-07-132-0/+448
| | | | llvm-svn: 108286
* AVX 256-bit conversion instructionsBruno Cardoso Lopes2010-07-132-0/+208
| | | | | | Add the x86 VEX_L form to handle special cases where VEX_L must be set. llvm-svn: 108274
* Add AVX 256-bit packed logical formsBruno Cardoso Lopes2010-07-132-0/+128
| | | | llvm-svn: 108224
* Add AVX 256-bit unop arithmetic instructionsBruno Cardoso Lopes2010-07-132-0/+64
| | | | llvm-svn: 108223
* Add AVX 256 binary arithmetic instructionsBruno Cardoso Lopes2010-07-122-0/+192
| | | | llvm-svn: 108207
* Add AVX 256-bit MOVMSK formsBruno Cardoso Lopes2010-07-122-0/+15
| | | | llvm-svn: 108184
* MC/AsmParser: Move .tbss and .zerofill parsing to Darwin specific parser.Daniel Dunbar2010-07-122-3/+1
| | | | llvm-svn: 108180
* MC/AsmParser: Move .desc parsing to Darwin specific parser.Daniel Dunbar2010-07-121-1/+1
| | | | llvm-svn: 108179
* MC/AsmParser: Move some misc. Darwin directive handling to DarwinAsmParser.Daniel Dunbar2010-07-122-4/+4
| | | | llvm-svn: 108174
* Add AVX 256-bit packed MOVNT variantsBruno Cardoso Lopes2010-07-092-0/+25
| | | | llvm-svn: 108021
* Add AVX 256-bit unpack and interleaveBruno Cardoso Lopes2010-07-092-0/+64
| | | | llvm-svn: 108017
* Start the support for AVX instructions with 256-bit %ymm registers. A couple ofBruno Cardoso Lopes2010-07-092-0/+98
| | | | | | | | | | | | | | | notes: - The instructions are being added with dummy placeholder patterns using some 256 specifiers, this is not meant to work now, but since there are some multiclasses generic enough to accept them, when we go for codegen, the stuff will be already there. - Add VEX encoding bits to support YMM - Add MOVUPS and MOVAPS in the first round - Use "Y" as suffix for those Instructions: MOVUPSYrr, ... - All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX file. llvm-svn: 107996
* Rework segment prefix emission code to handle segmentsChris Lattner2010-07-081-0/+5
| | | | | | | | | | | | in memory operands at the same type as hard coded segments. This fixes problems where we'd emit the segment override after the REX prefix on instructions like: mov %gs:(%rdi), %rax This fixes rdar://8127102. I have several cleanup patches coming next. llvm-svn: 107917
* Implement the major chunk of PR7195: support for 'callw'Chris Lattner2010-07-071-0/+5
| | | | | | | in the integrated assembler. Still some discussion to be done. llvm-svn: 107825
* Add more assembly opcodes for SSE compare instructionsBruno Cardoso Lopes2010-07-072-0/+190
| | | | llvm-svn: 107823
* Add AVX AES instructionsBruno Cardoso Lopes2010-07-072-0/+97
| | | | llvm-svn: 107798
* Add AVX SSE4.2 instructionsBruno Cardoso Lopes2010-07-072-0/+79
| | | | llvm-svn: 107752
* Add AVX SSE4.1 insertps, ptest and movntdqa instructionsBruno Cardoso Lopes2010-07-072-0/+40
| | | | llvm-svn: 107747
* Add AVX SSE4.1 extractps and pinsr instructionsBruno Cardoso Lopes2010-07-072-0/+72
| | | | llvm-svn: 107746
* Add AVX SSE4.1 Extract Integer instructionsBruno Cardoso Lopes2010-07-072-0/+56
| | | | llvm-svn: 107740
* Add the rest of AVX SSE4.1 packed move with sign/zero extend instructionsBruno Cardoso Lopes2010-07-062-0/+95
| | | | llvm-svn: 107723
* Add part of AVX SSE4.1 packed move with sign/zero extend instructionsBruno Cardoso Lopes2010-07-062-0/+97
| | | | llvm-svn: 107720
* Add AVX vblendvpd, vblendvps and vpblendvb instructionsBruno Cardoso Lopes2010-07-062-0/+47
| | | | | | Update VEX encoding to support those new instructions llvm-svn: 107715
* Add AVX SSE4.1 blend, mpsadbw and vdpBruno Cardoso Lopes2010-07-032-0/+113
| | | | llvm-svn: 107560
* Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructionsBruno Cardoso Lopes2010-07-032-0/+176
| | | | llvm-svn: 107558
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