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* Upgrade syntax of tests using volatile instructions to use 'load volatile' ↵Chris Lattner2011-11-271-6/+6
| | | | | | instead of 'volatile load', which is archaic. llvm-svn: 145171
* Remove obsolete test.Jim Grosbach2011-11-161-58/+0
| | | | | | The PLD encoding is checked via the .s file now. llvm-svn: 144853
* Generalize the fixup info for ARM mode.Jim Grosbach2011-11-161-2/+2
| | | | | | | We don't (yet) have the granularity in the fixups to be specific about which bitranges are affected. That's a future cleanup, but we're not there yet. llvm-svn: 144852
* Update test for r144842.Jim Grosbach2011-11-161-1/+1
| | | | llvm-svn: 144851
* ARM assembly parsing for register range syntax for VLD/VST register lists.Jim Grosbach2011-11-151-0/+8
| | | | | | | | | | | | | | | | For example, vld1.f64 {d2-d5}, [r2,:128]! Should be equivalent to: vld1.f64 {d2,d3,d4,d5}, [r2,:128]! It's not documented syntax in the ARM ARM, but it is consistent with what's accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to support. rdar://10451128 llvm-svn: 144727
* ARM assembly parsing two operand forms for shift instructions.Jim Grosbach2011-11-151-0/+8
| | | | llvm-svn: 144713
* ARM alternate size suffices for VTRN instructions.Jim Grosbach2011-11-151-0/+60
| | | | | | rdar://10435076 llvm-svn: 144694
* ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.Jim Grosbach2011-11-151-0/+10
| | | | | | Yet more of rdar://10435076. llvm-svn: 144691
* ARM assembly parsing for two-operand form of 'mul' instruction.Jim Grosbach2011-11-151-0/+6
| | | | | | rdar://10449856. llvm-svn: 144689
* ARM assembly parsing for two-operand form of 'mul' instruction.Jim Grosbach2011-11-151-0/+2
| | | | | | Ongoing rdar://10435114. llvm-svn: 144688
* Testcase for r144684.Jim Grosbach2011-11-151-0/+2
| | | | llvm-svn: 144685
* Thumb2 assembly parsing for mul.w in IT block fix.Jim Grosbach2011-11-151-0/+4
| | | | | | | | | | When the 3rd operand is not a low-register, and the first two operands are the same low register, the parser was incorrectly trying to use the 16-bit instruction encoding. rdar://10449281 llvm-svn: 144679
* ARM parsing datatype suffix variants for non-writeback VST1 instructions.Jim Grosbach2011-11-141-0/+21
| | | | | | rdar://10435076 llvm-svn: 144593
* ARM parsing datatype suffix variants for non-writeback VLD1 instructions.Jim Grosbach2011-11-141-0/+28
| | | | | | rdar://10435076 llvm-svn: 144592
* ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.Jim Grosbach2011-11-141-0/+177
| | | | | | rdar://10435076 llvm-svn: 144587
* ARM VLDR/VSTR instructions don't need a size suffix.Jim Grosbach2011-11-141-27/+27
| | | | | | | Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. llvm-svn: 144583
* ARM optional size suffix for VLDR/VSTR syntax.Jim Grosbach2011-11-111-0/+10
| | | | llvm-svn: 144427
* ARM allow Q registers in vldm/vstm register lists.Jim Grosbach2011-11-111-0/+2
| | | | | | rdar://9672822 llvm-svn: 144407
* Thumb2 parsing for push/pop w/ hi registers in the reglist.Jim Grosbach2011-11-101-0/+15
| | | | | | rdar://10130228. llvm-svn: 144331
* Thumb MUL assembly parsing for 3-operand form.Jim Grosbach2011-11-101-0/+2
| | | | | | | | | Get the source register that isn't tied to the destination register correct, even when the assembly source operand order is backwards. rdar://10428630 llvm-svn: 144322
* ARM assembly parsing for LSR/LSL/ROR(immediate).Jim Grosbach2011-11-102-6/+33
| | | | | | More of rdar://9704684 llvm-svn: 144301
* ARM assembly parsing for ASR(immediate).Jim Grosbach2011-11-101-1/+8
| | | | | | Start of rdar://9704684 llvm-svn: 144293
* Thumb2 assembly parsing STMDB w/ optional .w suffix.Jim Grosbach2011-11-091-0/+2
| | | | | | rdar://10422955 llvm-svn: 144242
* Simplify some uses of utohexstr.Benjamin Kramer2011-11-073-18/+18
| | | | | | As a side effect hex is printed lowercase instead of uppercase now. llvm-svn: 144013
* Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".Jim Grosbach2011-10-281-0/+7
| | | | | | | | | | | When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example, mov r2, #-3 becomes mvn r2, #2 rdar://10349224 llvm-svn: 143235
* Thumb2 ADD/SUB instructions encoding selection outside IT block.Jim Grosbach2011-10-282-2/+6
| | | | | | | | | | | Outside an IT block, "add r3, #2" should select a 32-bit wide encoding rather than generating an error indicating the 16-bit encoding is only legal in an IT block (outside, the 'S' suffic is required for the 16-bit encoding). rdar://10348481 llvm-svn: 143201
* ARM Allow 'q' registers in VLD/VST vector lists.Jim Grosbach2011-10-281-0/+9
| | | | | | | | Just treat it as if the constituent D registers where specified. rdar://10348896 llvm-svn: 143167
* Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix.Jim Grosbach2011-10-271-0/+4
| | | | | | rdar://10348844 llvm-svn: 143110
* Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.Jim Grosbach2011-10-271-2/+2
| | | | | | rdar://10348584 llvm-svn: 143108
* Thumb2 ldr pc-relative encoding fixes.Jim Grosbach2011-10-261-8/+11
| | | | | | | | | We were parsing label references to the i12 encoding, which isn't right. They need to go to the pci variant instead. More of rdar://10348687 llvm-svn: 143068
* ARM assembly parsing and encoding for VLD1 with writeback.Jim Grosbach2011-10-251-0/+20
| | | | | | Four entry register lists. llvm-svn: 142882
* ARM assembly parsing and encoding for VLD1 w/ writeback.Jim Grosbach2011-10-241-0/+20
| | | | | | Three entry register list variation. llvm-svn: 142876
* ARM assembly parsing and encoding for VLD1 w/ writeback.Jim Grosbach2011-10-241-11/+47
| | | | | | One and two length register list variants. llvm-svn: 142861
* Update test for r142801.Jim Grosbach2011-10-241-1/+1
| | | | llvm-svn: 142806
* Assembly parsing for 4-register sequential variant of VLD2.Jim Grosbach2011-10-211-6/+6
| | | | llvm-svn: 142704
* Assembly parsing for 2-register sequential variant of VLD2.Jim Grosbach2011-10-211-7/+7
| | | | llvm-svn: 142691
* Assembly parsing for 4-register variant of VLD1.Jim Grosbach2011-10-211-0/+9
| | | | llvm-svn: 142682
* Assembly parsing for 3-register variant of VLD1.Jim Grosbach2011-10-211-1/+8
| | | | llvm-svn: 142675
* ARM VLD parsing and encoding.Jim Grosbach2011-10-211-8/+8
| | | | | | | | | | | | Next step in the ongoing saga of NEON load/store assmebly parsing. Handle VLD1 instructions that take a two-register register list. Adjust the instruction definitions to only have the single encoded register as an operand. The super-register from the pseudo is kept as an implicit def, so passes which come after pseudo-expansion still know that the instruction defines the other subregs. llvm-svn: 142670
* Revert r142618, r142622, and r142624, which were based on an incorrect ↵Owen Anderson2011-10-201-18/+18
| | | | | | reading of the ARMv7 docs. llvm-svn: 142626
* Fix tests for corrected MSR encodings.Owen Anderson2011-10-201-18/+18
| | | | llvm-svn: 142622
* ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding.Jim Grosbach2011-10-202-224/+222
| | | | llvm-svn: 142583
* Tidy up formatting.Jim Grosbach2011-10-201-46/+59
| | | | llvm-svn: 142582
* ARM VTBX (one register) assembly parsing and encoding.Jim Grosbach2011-10-201-13/+12
| | | | llvm-svn: 142581
* Tidy up formatting.Jim Grosbach2011-10-181-8/+12
| | | | llvm-svn: 142422
* Tidy up formatting.Jim Grosbach2011-10-181-8/+12
| | | | llvm-svn: 142421
* Enable more encoded immediate tests.Jim Grosbach2011-10-181-5/+5
| | | | llvm-svn: 142415
* More vmov lane testcases.Jim Grosbach2011-10-181-22/+22
| | | | llvm-svn: 142414
* ARM vmla/vmls assembly parsing for the lane index operand.Jim Grosbach2011-10-181-4/+4
| | | | llvm-svn: 142413
* ARM vmov assembly parsing for the lane index operand.Jim Grosbach2011-10-181-22/+22
| | | | llvm-svn: 142412
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