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* ARM NEON relax parse time diagnostics for alignment specifiers.Jim Grosbach2011-12-191-8/+8
| | | | | | | There's more variation that we need to handle. Error checking will need to be on operand predicates. llvm-svn: 146884
* ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.Jim Grosbach2011-12-151-0/+30
| | | | llvm-svn: 146699
* ARM NEON VTBL/VTBX assembly parsing and encoding.Jim Grosbach2011-12-152-21/+20
| | | | llvm-svn: 146691
* ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.Jim Grosbach2011-12-142-4/+19
| | | | llvm-svn: 146605
* ARM NEON fix alignment encoding for VST2 w/ writeback.Jim Grosbach2011-12-141-0/+12
| | | | | | Add tests for w/ writeback instruction parsing and encoding. llvm-svn: 146594
* ARM NEON VST2 assembly parsing and encoding.Jim Grosbach2011-12-141-13/+13
| | | | | | | | Work in progress. Parsing for non-writeback, single spaced register lists works now. The rest have the representations better factored, but still need more to be able to parse properly. llvm-svn: 146579
* ARM/Thumb2 'cmp rn, #imm' alias to cmn.Jim Grosbach2011-12-142-1/+4
| | | | | | | | | | When 'cmp rn #imm' doesn't match due to the immediate not being representable, but 'cmn rn, #-imm' does match, use the latter in place of the former, as it's equivalent. rdar://10552389 llvm-svn: 146567
* ARM assembler support for the target-specific .req directive.Jim Grosbach2011-12-141-0/+11
| | | | | | rdar://10549683 llvm-svn: 146543
* Thumb2 assembler aliases for "mov(shifted register)"Jim Grosbach2011-12-131-0/+12
| | | | | | rdar://10549767 llvm-svn: 146520
* ARM LDM/STM system instruction variants.Jim Grosbach2011-12-131-0/+6
| | | | | | rdar://10550269 llvm-svn: 146519
* Test for 146516Jim Grosbach2011-12-131-0/+4
| | | | llvm-svn: 146517
* ARM thumb2 parsing of "rsb rd, rn, #0".Jim Grosbach2011-12-131-0/+4
| | | | | | rdar://10549741 llvm-svn: 146515
* ARM NEON two-operand aliases for VQDMULH.Jim Grosbach2011-12-131-0/+8
| | | | llvm-svn: 146514
* ARM pre-UAL NEG mnemonic for convenience when porting old code.Jim Grosbach2011-12-132-0/+18
| | | | llvm-svn: 146511
* ARM assembly aliases for BIC<-->AND (immediate).Jim Grosbach2011-12-091-0/+2
| | | | | | | | | | | When the immediate operand of an AND or BIC instruction isn't representable in the immediate field of the instruction, but the bitwise negation of the immediate is, assemble the instruction as the inverse operation instead with the inverted immediate as the operand. rdar://10550057 llvm-svn: 146283
* ARM assembly parsing and encoding for VLD2 with writeback.Jim Grosbach2011-12-091-0/+28
| | | | | | | | | | | Refactor the instructions into fixed writeback and register-stride writeback variants to simplify the offset operand (no more optional register operand using reg0). This is a simpler representation and allows the assembly parser to more easily handle these instructions. Add tests for the instruction variants now supported. llvm-svn: 146278
* ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.Jim Grosbach2011-12-081-0/+4
| | | | llvm-svn: 146194
* ARM VSHR implied destination operand form aliases.Jim Grosbach2011-12-081-0/+35
| | | | llvm-svn: 146192
* Tidy up a bit.Jim Grosbach2011-12-081-32/+37
| | | | llvm-svn: 146190
* ARM VSUB implied destination operand form aliases.Jim Grosbach2011-12-081-1/+24
| | | | llvm-svn: 146182
* Tidy up a bit.Jim Grosbach2011-12-081-10/+13
| | | | llvm-svn: 146181
* ARM VQADD implied destination operand form aliases.Jim Grosbach2011-12-081-16/+58
| | | | llvm-svn: 146179
* ARM a few more VMUL implied destination operand form aliases.Jim Grosbach2011-12-081-1/+22
| | | | llvm-svn: 146177
* ARM NEON two-operand aliases for VSHL(immediate).Jim Grosbach2011-12-081-0/+20
| | | | llvm-svn: 146125
* ARM NEON two-operand aliases for VSHL(register).Jim Grosbach2011-12-081-0/+41
| | | | llvm-svn: 146123
* ARM optional destination operand variants for VEXT instructions.Jim Grosbach2011-12-081-0/+15
| | | | llvm-svn: 146114
* Tidy up.Jim Grosbach2011-12-081-22/+29
| | | | llvm-svn: 146113
* ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".Jim Grosbach2011-12-081-1/+6
| | | | llvm-svn: 146111
* ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.Jim Grosbach2011-12-071-0/+2
| | | | | | For 'gas' compatibility. llvm-svn: 146106
* ARM two-operand aliases for VAND/VEOR/VORR instructions.Jim Grosbach2011-12-071-0/+31
| | | | llvm-svn: 146095
* ARM two-operand aliases for VADDW instructions.Jim Grosbach2011-12-071-0/+17
| | | | llvm-svn: 146093
* ARM two-operand aliases for VADD instructions.Jim Grosbach2011-12-071-0/+23
| | | | llvm-svn: 146091
* Thumb2 alias for long-form pop and friends.Jim Grosbach2011-12-071-0/+2
| | | | | | rdar://10542474 llvm-svn: 146046
* ARM support the .arm and .thumb directives for assembly mode switching.Jim Grosbach2011-12-071-0/+11
| | | | llvm-svn: 146042
* ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).Jim Grosbach2011-12-071-0/+33
| | | | llvm-svn: 146039
* Tidy up. Move MachO tests to MachO directory.Jim Grosbach2011-12-077-371/+0
| | | | llvm-svn: 146038
* test/MC: Introduce MC/MachO/ARM, and relocate relax-thumb2-branches.s into it.NAKAMURA Takumi2011-12-061-14/+0
| | | | | FIXME: Restore more other arch-dependent MachO tests. (eg. r126401 and r133856) llvm-svn: 145925
* ARM mode 'mul' operand ordering tweak.Jim Grosbach2011-12-061-1/+0
| | | | | | Same as r145922, just for ARM mode. llvm-svn: 145923
* Thumb2: MUL two-operand form encoding operand order fix.Jim Grosbach2011-12-061-2/+2
| | | | | | | | | Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we match gas. rdar://10532439 llvm-svn: 145922
* Thumb2 encoding choice correction for PLD.Jim Grosbach2011-12-061-0/+4
| | | | | | | | Using encoding T1 for offset of #0 and encoding T2 for #-0. rdar://10532413 llvm-svn: 145919
* test/MC: Move relax-thumb2-branches.s from MC/MachO/ to MC/ARM.NAKAMURA Takumi2011-12-061-0/+14
| | | | | | MC/MachO assumes x86. llvm-svn: 145916
* Tweak ADDrr fix. Bad check for explicit .wJim Grosbach2011-12-051-1/+1
| | | | llvm-svn: 145863
* Update tests for r145860. Add a few new ones.Jim Grosbach2011-12-052-1/+5
| | | | llvm-svn: 145861
* Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.Jim Grosbach2011-12-051-0/+4
| | | | | | rdar://10529348 llvm-svn: 145851
* ARM assembly parsing for the rest of the VMUL data type aliases.Jim Grosbach2011-12-051-0/+65
| | | | | | Finish up rdar://10522016. llvm-svn: 145846
* ARM tests for VLD1 single lane w/ writeback.Jim Grosbach2011-12-021-0/+8
| | | | llvm-svn: 145713
* Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.Jim Grosbach2011-12-021-2/+2
| | | | | | Add the 16-bit lane variants while I'm at it. llvm-svn: 145693
* Add some tests for all-lanes VLD1 parsing.Jim Grosbach2011-11-301-0/+14
| | | | llvm-svn: 145512
* ARM assembly parsing and encoding for four-register VST1.Jim Grosbach2011-11-291-0/+6
| | | | llvm-svn: 145450
* Enable some VST1 tests and add a few more.Jim Grosbach2011-11-291-14/+20
| | | | llvm-svn: 145443
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