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* Ensure conditional BL instructions for ARM are given the fixup ↵James Molloy2012-03-303-2/+28
| | | | | | | | fixup_arm_condbranch. Patch by Tim Northover! llvm-svn: 153737
* ARM assembly 'cmp lr, #0' should not encode using 'cmn'.Jim Grosbach2012-03-291-0/+2
| | | | | | | | | The CMP->CMN alias was matching for an immediate of zero when it should only match for negative values. rdar://11129224 llvm-svn: 153689
* Fixup VST1.32 with writeback instruction. Also re-factor non-writeback version.Richard Barton2012-03-281-0/+8
| | | | llvm-svn: 153573
* Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnuEli Bendersky2012-03-251-8/+1
| | | | | | | | | | | | | | * Removed test/lib/llvm.exp - it is no longer needed * Deleted the dg.exp reading code from test/lit.cfg. There are no dg.exp files left in the test suite so this code is no longer required. test/lit.cfg is now much shorter and clearer * Removed a lot of duplicate code in lit.local.cfg files that need access to the root configuration, by adding a "root" attribute to the TestingConfig object. This attribute is dynamically computed to provide the same information as was previously provided by the custom getRoot functions. * Documented the config.root attribute in docs/CommandGuide/lit.pod llvm-svn: 153408
* Fix assembling ARM vst2 instructions with double-spaced registers.Kevin Enderby2012-03-202-0/+8
| | | | llvm-svn: 153099
* ARM ldm/stm register lists can be out of order.Jim Grosbach2012-03-161-1/+1
| | | | | | | | | | It's not a good style idea, as the registers will be laid down in memory in numerical order, not the order they're in the list, but it's legal. vldm/vstm are stricter. rdar://11064740 llvm-svn: 152943
* ARM optional operand on MRC/MCR assembly instructions.Jim Grosbach2012-03-161-0/+8
| | | | | | rdar://11058464 llvm-svn: 152883
* ARM vmrs system registers mvfr0 and mvfr1 handling.Jim Grosbach2012-03-161-3/+12
| | | | | | rdar://11058464 llvm-svn: 152881
* ARM case-insensitive checking for APSR_nzcv.Jim Grosbach2012-03-151-2/+4
| | | | | | rdar://11056591 llvm-svn: 152846
* Fix VCVT decoding (between floating-point and fixed-point, Floating-point). ↵Kristof Beyls2012-03-151-1/+26
| | | | | | Patch by Richard Barton. llvm-svn: 152814
* ARM vpush/vpop assembler mnemonics accept an optional size suffix.Jim Grosbach2012-03-051-0/+15
| | | | | | rdar://10988114 llvm-svn: 152068
* ARM BL/BLX instruction fixups should use relocations.Jim Grosbach2012-02-272-3/+3
| | | | | | | | | | | | | We on the linker to resolve calls to the appropriate BL/BLX instruction to make interworking function correctly. It uses the symbol in the relocation to do that, so we need to be careful about being too clever. To enable this for ARM mode, split the BL/BLX fixup kind off from the unconditional-branch fixups. rdar://10927209 llvm-svn: 151571
* Replace all instances of dg.exp file with lit.local.cfg, since all tests are ↵Eli Bendersky2012-02-162-5/+13
| | | | | | | | run with LIT now and now Dejagnu. dg.exp is no longer needed. Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches. llvm-svn: 150664
* Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM ↵James Molloy2012-01-281-0/+6
| | | | | | | | and MIPS ELF backends. Fixes PR11877 llvm-svn: 149180
* Add support for the R_ARM_TARGET1 relocation, which should be given to ↵James Molloy2012-01-261-0/+12
| | | | | | | | relocations applied to all C++ constructors and destructors. This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against. llvm-svn: 149057
* ARM assemly parsing and validation of IT instruction.Jim Grosbach2012-01-251-0/+11
| | | | | | | | | | "Although a Thumb2 instruction, the IT mnemonic shall be permitted in ARM mode, and the condition verified to match the condition code(s) on the following instruction(s)." PR11853 llvm-svn: 148969
* NEON VLD4(all lanes) assembly parsing and encoding.Jim Grosbach2012-01-251-0/+40
| | | | llvm-svn: 148884
* NEON VLD3(all lanes) assembly parsing and encoding.Jim Grosbach2012-01-241-0/+41
| | | | llvm-svn: 148882
* NEON VST4(one lane) assembly parsing and encoding.Jim Grosbach2012-01-241-11/+33
| | | | llvm-svn: 148836
* NEON VLD4(one lane) assembly parsing and encoding.Jim Grosbach2012-01-241-11/+33
| | | | llvm-svn: 148832
* NEON Two-operand assembly aliases for VSRA.Jim Grosbach2012-01-241-33/+71
| | | | llvm-svn: 148821
* Remove redundant test file.Jim Grosbach2012-01-241-98/+0
| | | | llvm-svn: 148820
* NEON Two-operand assembly aliases for VSLI.Jim Grosbach2012-01-241-16/+33
| | | | llvm-svn: 148819
* NEON Two-operand assembly aliases for VSRI.Jim Grosbach2012-01-241-16/+33
| | | | llvm-svn: 148818
* Tidy up.Jim Grosbach2012-01-241-32/+41
| | | | llvm-svn: 148817
* NEON VST4(multiple 4 element structures) assembly parsing.Jim Grosbach2012-01-241-17/+39
| | | | llvm-svn: 148764
* NEON VLD4(multiple 4 element structures) assembly parsing.Jim Grosbach2012-01-241-19/+39
| | | | llvm-svn: 148762
* NEON VST3(single element from one lane) assembly parsing.Jim Grosbach2012-01-241-0/+35
| | | | llvm-svn: 148755
* NEON VST3(multiple 3-element structures) assembly parsing.Jim Grosbach2012-01-231-19/+39
| | | | llvm-svn: 148748
* NEON VLD3(multiple 3-element structures) assembly parsing.Jim Grosbach2012-01-232-65/+73
| | | | llvm-svn: 148745
* NEON VLD3 lane-indexed assembly parsing and encoding.Jim Grosbach2012-01-231-11/+33
| | | | llvm-svn: 148734
* Simplify some NEON assembly pseudo definitions.Jim Grosbach2012-01-231-8/+8
| | | | | | | Let the generic token alias definitions handle the data subtype suffices. We don't need explicit versions for each. llvm-svn: 148718
* NEON use vmov.i32 to splat some f32 values into vectors.Jim Grosbach2012-01-201-0/+8
| | | | | | | | | | | For bit patterns that aren't representable using the 8-bit floating point representation for vmov.f32, but are representable via vmov.i32, treat the .f32 syntax as an alias. Most importantly, this covers the case 'vmov.f32 Vd, #0.0'. rdar://10616677 llvm-svn: 148556
* Thumb2 alternate syntax for LDR(literal) and friends.Jim Grosbach2012-01-181-0/+27
| | | | | | | | Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]". rdar://10250964 llvm-svn: 148432
* ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).Jim Grosbach2011-12-221-0/+12
| | | | | | rdar://10558523 llvm-svn: 147189
* Fix incorrect relocation generation. Patch by Kristof Beyls.Rafael Espindola2011-12-221-0/+23
| | | | | | Fixes PR11214. llvm-svn: 147180
* ARM assembler should accept shift-by-zero for any shifted-immediate operand.Jim Grosbach2011-12-221-0/+17
| | | | | | | | Just treat it as-if the shift wasn't there at all. 'as' compatibility. rdar://10604767 llvm-svn: 147153
* ARM VFP optional data type on VMOV GPR<-->SPR.Jim Grosbach2011-12-211-0/+28
| | | | llvm-svn: 147104
* Thumb2 assembly parsing of 'mov rd, rn, rrx'.Jim Grosbach2011-12-211-1/+2
| | | | | | | | Maps to the RRX instruction. Missed this case earlier. rdar://10615373 llvm-svn: 147096
* Thumb2 assembly parsing of 'mov(register shifted register)' aliases.Jim Grosbach2011-12-211-0/+25
| | | | | | | | These map to the ASR, LSR, LSL, ROR instruction definitions. rdar://10615373 llvm-svn: 147094
* ARM NEON assmebly parsing for VLD2 to all lanes instructions.Jim Grosbach2011-12-211-0/+8
| | | | llvm-svn: 147069
* ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.Jim Grosbach2011-12-211-1/+4
| | | | llvm-svn: 147025
* Enable and fix a test.Jim Grosbach2011-12-201-2/+2
| | | | llvm-svn: 147011
* ARM assembly parsing and encoding for VST2 single-element, double spaced.Jim Grosbach2011-12-201-4/+18
| | | | llvm-svn: 146990
* ARM enable a few more tests.Jim Grosbach2011-12-201-4/+4
| | | | llvm-svn: 146985
* ARM assembly parsing and encoding for VLD2 single-element, double spaced.Jim Grosbach2011-12-201-4/+6
| | | | llvm-svn: 146983
* ARM assembly shifts by zero should be plain 'mov' instructions.Jim Grosbach2011-12-201-0/+17
| | | | | | | | | | "mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's not strictly legal UAL syntax. It's a common extension and the friendly thing to do. rdar://10604663 llvm-svn: 146937
* ARM assembly parsing and encoding support for LDRD(label).Jim Grosbach2011-12-191-1/+6
| | | | | | rdar://9932658 llvm-svn: 146921
* ARM NEON two-operand aliases for VPADD.Jim Grosbach2011-12-191-0/+10
| | | | | | rdar://10602276 llvm-svn: 146895
* ARM NEON implied destination aliases for VMAX/VMIN.Jim Grosbach2011-12-192-110/+242
| | | | llvm-svn: 146885
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