summaryrefslogtreecommitdiffstats
path: root/llvm/test/MC/ARM
Commit message (Collapse)AuthorAgeFilesLines
...
* Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset ↵Jiangning Liu2012-08-021-0/+12
| | | | | | index issue. llvm-svn: 161162
* Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.Jiangning Liu2012-08-022-0/+142
| | | | llvm-svn: 161161
* Fix #13241, a bug around shift immediate operand for ARM instruction ADR.Jiangning Liu2012-08-022-0/+10
| | | | llvm-svn: 161159
* Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton2012-07-101-0/+21
| | | | | | single-precision resiters) (and do it properly this time! llvm-svn: 159989
* Revert r159938 (and r159945) to appease the buildbots.Chad Rosier2012-07-091-21/+0
| | | | llvm-svn: 159960
* Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton2012-07-091-0/+21
| | | | | | single-precision resiters) llvm-svn: 159938
* Prevent ARM assembler from losing a right shift by #32 applied to a registerRichard Barton2012-07-091-0/+33
| | | | llvm-svn: 159937
* Teach the assembler to use the narrow thumb encodings of various ↵Richard Barton2012-07-091-0/+807
| | | | | | three-register dp instructions where permissable. llvm-svn: 159935
* Teach assembler to handle capitalised operation values for DSB instructionsRichard Barton2012-06-271-0/+6
| | | | llvm-svn: 159259
* ARM: Add a better diagnostic for some out of range immediates.Jim Grosbach2012-06-222-8/+8
| | | | | | | | | | | As an example of how the custom DiagnosticType can be used to provide better operand-mismatch diagnostics, add a custom diagnostic for the imm0_15 operand class used for several system instructions. Update the tests to expect the improved diagnostic. rdar://8987109 llvm-svn: 159051
* Have ARM ELF use correct reloc for "b" instr.Jan Wen Voung2012-06-191-1/+11
| | | | | | | The condition code didn't actually matter for arm "b" instructions, unlike "bl". It should just use the R_ARM_JUMP24 reloc. llvm-svn: 158722
* ARM: Define generic HINT instruction.Jim Grosbach2012-06-182-8/+34
| | | | | | | | | | | The NOP, WFE, WFI, SEV and YIELD instructions are all hints w/ a different immediate value in bits [7,0]. Define a generic HINT instruction and refactor NOP, WFI, WFI, SEV and YIELD to be assembly aliases of that. rdar://11600518 llvm-svn: 158674
* Fix the encoding of the armv7m (MClass) for MSR registers other than aspr,Kevin Enderby2012-06-151-10/+10
| | | | | | iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits. llvm-svn: 158560
* Replace assertion failure for badly formatted CPS instrution with error message.Richard Barton2012-06-141-0/+6
| | | | llvm-svn: 158445
* Refactor data-in-code annotations.Jim Grosbach2012-05-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | Use a dedicated MachO load command to annotate data-in-code regions. This is the same format the linker produces for final executable images, allowing consistency of representation and use of introspection tools for both object and executable files. Data-in-code regions are annotated via ".data_region"/".end_data_region" directive pairs, with an optional region type. data_region_directive := ".data_region" { region_type } region_type := "jt8" | "jt16" | "jt32" | "jta32" end_data_region_directive := ".end_data_region" The previous handling of ARM-style "$d.*" labels was broken and has been removed. Specifically, it didn't handle ARM vs. Thumb mode when marking the end of the section. rdar://11459456 llvm-svn: 157062
* Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missingKevin Enderby2012-05-171-4/+28
| | | | | | | | | | the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in the code for better error checking when versions shouldn't be used. rdar://11457025 llvm-svn: 157019
* Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate ↵Silviu Baranga2012-05-111-0/+3
| | | | | | offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate. llvm-svn: 156608
* Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bitsKevin Enderby2012-05-031-2/+2
| | | | | | | | | for the assembler and disassembler. Which were not being set/read correctly for offsets greater than 22 bits in some cases. Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles! llvm-svn: 156118
* ARM: Add missing two-operand VBIC aliases.Jim Grosbach2012-05-021-0/+5
| | | | llvm-svn: 156019
* Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.Richard Barton2012-05-023-17/+18
| | | | llvm-svn: 155983
* ARM: Add a few missing add->sub aliases w/ 'w' suffix.Jim Grosbach2012-05-011-0/+12
| | | | | | | | | | | | | | Aliases for adding a negative immediate when using an explicit 'w' suffix. E.g., adds.w r2, #-16 adds.w r2, r2, #-16 addw r2, #-16 addw r2, #-16 addw r2, r2, #-16 rdar://11330769 llvm-svn: 155946
* ARM: allow vanilla expressions for movw/movt.Jim Grosbach2012-05-011-0/+5
| | | | | | | | | | Expressions for movw/movt don't always have an :upper16: or :lower16: on them and that's ok. When they don't, it's just a plain [0-65536] immediate result, effectively the same as a :lower16: variant kind. rdar://10550147 llvm-svn: 155941
* ARM: Thumb add(sp plus register) asm constraints.Jim Grosbach2012-04-272-0/+7
| | | | | | | | | | Make sure when parsing the Thumb1 sp+register ADD instruction that the source and destination operands match. In thumb2, just use the wide encoding if they don't. In Thumb1, issue a diagnostic. rdar://11219154 llvm-svn: 155748
* Fix ARM assembly parsing for upper case condition codes on IT instructions.Richard Barton2012-04-271-0/+13
| | | | llvm-svn: 155720
* Specify cpu to unbreak tests.Evan Cheng2012-04-265-6/+6
| | | | llvm-svn: 155604
* ARM: improved assembler diagnostics for missing CPU features.Jim Grosbach2012-04-241-9/+9
| | | | | | | | | | | When an instruction match is found, but the subtarget features it requires are not available (missing floating point unit, or thumb vs arm mode, for example), issue a diagnostic that identifies what the feature mismatch is. rdar://11257547 llvm-svn: 155499
* ARM: Add testcases for two-operand variants of VSRA/VRSRA/VSRI.Jim Grosbach2012-04-232-0/+209
| | | | llvm-svn: 155391
* Add ARM mode tests for the NEON vector shift-accumulate tests.Jim Grosbach2012-04-231-0/+105
| | | | llvm-svn: 155390
* Tidy up. Reformat for ease of reading.Jim Grosbach2012-04-231-95/+102
| | | | llvm-svn: 155389
* ARM: Update NEON assembly two-operand aliases.Jim Grosbach2012-04-202-0/+21
| | | | | | | | Use the new TwoOperandAliasConstraint to handle lots of the two-operand aliases for NEON instructions. There's still more to go, but this is a good chunk of them. llvm-svn: 155210
* ARM some VFP tblgen'erated two-operand aliases.Jim Grosbach2012-04-201-2/+7
| | | | llvm-svn: 155178
* Tidy up. Formatting.Jim Grosbach2012-04-201-53/+45
| | | | llvm-svn: 155177
* ARM two-operand forms for vhadd and vhsub instructions.Jim Grosbach2012-04-162-0/+53
| | | | | | rdar://11252521 llvm-svn: 154875
* ARM assembly two-operand forms for VRSHL.Jim Grosbach2012-04-161-0/+35
| | | | | | rdar://11252521 llvm-svn: 154840
* Tidy up. Test formatting.Jim Grosbach2012-04-161-53/+64
| | | | llvm-svn: 154839
* ARM two-operand aliases for VRHADD instructions.Jim Grosbach2012-04-161-0/+27
| | | | | | rdar://11252521 llvm-svn: 154832
* Tidy up. Testcase formatting.Jim Grosbach2012-04-161-13/+14
| | | | llvm-svn: 154831
* ARM 'vuzp.32 Dd, Dm' is a pseudo-instruction.Jim Grosbach2012-04-111-0/+2
| | | | | | | | | | While there is an encoding for it in VUZP, the result of that is undefined, so we should avoid it. Define the instruction as a pseudo for VTRN.32 instead, as the ARM ARM indicates. rdar://11222366 llvm-svn: 154511
* ARM 'vzip.32 Dd, Dm' is a pseudo-instruction.Jim Grosbach2012-04-111-0/+2
| | | | | | | | | | While there is an encoding for it in VZIP, the result of that is undefined, so we should avoid it. Define the instruction as a pseudo for VTRN.32 instead, as the ARM ARM indicates. rdar://11221911 llvm-svn: 154505
* Clean up ARM fused multiply + add/sub support some more: rename some iselEvan Cheng2012-04-111-1/+1
| | | | | | | | | | | predicates. Also remove NEON2 since it's not really useful and it is confusing. If NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it really mean? rdar://10139676 llvm-svn: 154480
* ARM add missing Thumb1 two-operand aliases for shift-by-immediate.Jim Grosbach2012-04-111-0/+18
| | | | | | rdar://11222742 llvm-svn: 154457
* Fix a number of problems with ARM fused multiply add/subtract instructions.Evan Cheng2012-04-111-0/+50
| | | | | | | | | | 1. The new instruction itinerary entries are not properly described. 2. The asm parser can't handle vfms and vfnms. 3. There were no assembler, disassembler test cases. 4. HasNEON2 has the wrong assembler predicate. rdar://10139676 llvm-svn: 154456
* ARM fix cc_out operand handling for t2SUBrr instructions.Jim Grosbach2012-04-101-0/+12
| | | | | | | | | | | | We were incorrectly conflating some add variants which don't have a cc_out operand with the mirroring sub encodings, which do. Part of the awesome non-orthogonality legacy of thumb1. Similarly, handling of add/sub of an immediate was sometimes incorrectly removing the cc_out operand for add/sub register variants. rdar://11216577 llvm-svn: 154411
* ARM assembly aliases for add negative immediates using sub.Jim Grosbach2012-04-051-0/+4
| | | | | | | | | | 'add r2, #-1024' should just use 'sub r2, #1024' rather than erroring out. Thumb1 aliases for adding a negative immediate to the stack pointer, also. rdar://11192734 llvm-svn: 154123
* ARM assembly aliases for two-operand V[R]SHR instructions.Jim Grosbach2012-04-051-0/+70
| | | | | | rdar://11189467 llvm-svn: 154087
* ARM assembly parsing for 'msr' plain 'cpsr' operand.Jim Grosbach2012-04-051-0/+2
| | | | | | | | Plain 'cpsr' is an alias for 'cpsr_fc'. rdar://11153753 llvm-svn: 154080
* ARM assembler should prefer non-aliases encoding of cmp.Jim Grosbach2012-03-301-2/+5
| | | | | | | | When an immediate is both a value [t2_]so_imm and a [t2_]so_imm_neg, we want to use the non-negated form to make sure we prefer the normal encoding, not the aliased encoding via the negation of, e.g., 'cmp.w'. llvm-svn: 153770
* ARM encoding for VSWP got the second operand incorrect.Jim Grosbach2012-03-301-0/+7
| | | | | | | | | Make the non-tied register operand names line up with what the base class encoding handler expects. rdar://11157236 llvm-svn: 153766
* ARM integrated assembler should encoding choice for add/sub imm.Jim Grosbach2012-03-301-0/+8
| | | | | | | | | For 'adds r2, r2, #56' outside of an IT block, the 16-bit encoding T2 can be used for this syntax. Prefer the narrow encoding when possible. rdar://11156277 llvm-svn: 153759
* ARM assembly parsing needs to be paranoid about negative immediates.Jim Grosbach2012-03-301-1/+4
| | | | | | | | Make sure to treat immediates as unsigned when doing relative comparisons. rdar://11153621 llvm-svn: 153753
OpenPOWER on IntegriCloud