summaryrefslogtreecommitdiffstats
path: root/llvm/test/MC/ARM
Commit message (Collapse)AuthorAgeFilesLines
...
* ARM: bkpt has an implicit immediate constant 0Saleem Abdulrasool2013-12-231-0/+32
| | | | | | | | | The bkpt mnemonic has an implicit immediate constant of 0 unless otherwise specified. Add an instruction alias for the unvalued breakpoint mnemonic to treat it as a 0. This improves compatibility with GNU AS. Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org> llvm-svn: 197913
* ARM IAS: add support for the .pool directiveSaleem Abdulrasool2013-12-201-0/+18
| | | | | | | The .pool directive is an alias for the .ltorg directive used to create a literal pool. Simply treat .pool as if .ltorg was passed. llvm-svn: 197787
* Implement the .ltorg directive for ARM assemblyDavid Peixotto2013-12-192-0/+289
| | | | | | | | | | | | This directive will write out the assembler-maintained constant pool for the current section. These constant pools are created to support the ldr-pseudo instruction (e.g. ldr r0, =val). The directive can be used by the programmer to place the constant pool in a location that can be reached by a pc-relative offset in the ldr instruction. llvm-svn: 197711
* Implement the ldr-pseudo opcode for ARM assemblyDavid Peixotto2013-12-194-0/+489
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ldr-pseudo opcode is a convenience for loading 32-bit constants. It is converted into a pc-relative load from a constant pool. For example, ldr r0, =0x10001 ldr r1, =bar will generate this output in the final assembly ldr r0, .Ltmp0 ldr r1, .Ltmp1 ... .Ltmp0: .long 0x10001 .Ltmp1: .long bar Sketch of the LDR pseudo implementation: Keep a map from Section => ConstantPool When parsing ldr r0, =val parse val as an MCExpr get ConstantPool for current Section Label = CreateTempSymbol() remember val in ConstantPool at next free slot add operand to ldr that is MCSymbolRef of Label On finishParse() callback Write out all non-empty constant pools for each Entry in ConstantPool Emit Entry.Label Emit Entry.Value Possible improvements to be added in a later patch: 1. Does not convert load of small constants to mov (e.g. ldr r0, =0x1 => mov r0, 0x1) 2. Does reuse constant pool entries for same constant The implementation was tested for ARM, Thumb1, and Thumb2 targets on linux and darwin. llvm-svn: 197708
* ARM IAS: support .inst directiveSaleem Abdulrasool2013-12-198-0/+184
| | | | | | | | | This adds support for the .inst directive. This is an ARM specific directive to indicate an instruction encoded as a constant expression. The major difference between .word, .short, or .byte and .inst is that the latter will be disassembled as an instruction since it does not get flagged as data. llvm-svn: 197657
* [arm] Pass -triple to llvm-mc for ARM ELF test cases.Logan Chien2013-12-1122-44/+44
| | | | | | | Replace -arch with -triple so that we can guarantee that ELF object files can be generated. llvm-svn: 197062
* [arm] Implement ARM .arch directive.Logan Chien2013-12-1122-0/+662
| | | | llvm-svn: 197052
* Integrated assembler incorrectly lexes ARM-style commentsDavid Peixotto2013-12-061-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | The integrated assembler fails to properly lex arm comments when they are adjacent to an identifier in the input stream. The reason is that the arm comment symbol '@' is also used as symbol variant in other assembly languages so when lexing an identifier it allows the '@' symbol as part of the identifier. Example: $ cat comment.s foo: add r0, r0@got to parse this as a comment $ llvm-mc -triple armv7 comment.s comment.s:4:18: error: unexpected token in argument list add r0, r0@got to parse this as a comment ^ This should be parsed as correctly as `add r0, r0`. This commit modifes the assembly lexer to not include the '@' symbol in identifiers when lexing for targets that use '@' for comments. llvm-svn: 196607
* Move llvm/test/MC/ELF/thumb-st_other.s to test/MC/ARM.NAKAMURA Takumi2013-12-051-0/+19
| | | | llvm-svn: 196457
* Add support for parsing ARM symbol variants on ELF targetsDavid Peixotto2013-12-042-0/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM symbol variants are written with parens instead of @ like this: .word __GLOBAL_I_a(target1) This commit adds support for parsing these symbol variants in expressions. We introduce a new flag to MCAsmInfo that indicates the parser should use parens to parse the symbol variant. The expression parser is modified to look for symbol variants using parens instead of @ when the corresponding MCAsmInfo flag is true. The MCAsmInfo parens flag is enabled only for ARM on ELF. By adding this flag to MCAsmInfo, we are able to get rid of redundant ARM-specific symbol variants and use the generic variants instead (e.g. VK_GOT instead of VK_ARM_GOT). We use the new UseParensForSymbolVariant attribute in MCAsmInfo to correctly print the symbol variants for arm. To achive this we need to keep a handle to the MCAsmInfo in the MCSymbolRefExpr class that we can check when printing the symbol variant. Updated Tests: Changed case of symbol variant to match the generic kind. test/CodeGen/ARM/tls-models.ll test/CodeGen/ARM/tls1.ll test/CodeGen/ARM/tls2.ll test/CodeGen/Thumb2/tls1.ll test/CodeGen/Thumb2/tls2.ll PR18080 llvm-svn: 196424
* ARM integrated assembler generates incorrect nop opcodeDavid Peixotto2013-11-252-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a bug in the assembler that was causing bad code to be emitted. When switching modes in an assembly file (e.g. arm to thumb mode) we would always emit the opcode from the original mode. Consider this small example: $ cat align.s .code 16 foo: add r0, r0 .align 3 add r0, r0 $ llvm-mc -triple armv7-none-linux align.s -filetype=obj -o t.o $ llvm-objdump -triple thumbv7 -d t.o Disassembly of section .text: foo: 0: 00 44 add r0, r0 2: 00 f0 20 e3 blx #4195904 6: 00 00 movs r0, r0 8: 00 44 add r0, r0 This shows that we have actually emitted an arm nop (e320f000) instead of a thumb nop. Unfortunately, this encodes to a thumb branch which causes bad things to happen when compiling assembly code with align directives. The fix is to notify the ARMAsmBackend when we switch mode. The MCMachOStreamer was already doing this correctly. This patch makes the same change for the MCElfStreamer. There is still a bug in the way nops are emitted for alignment because the MCAlignment fragment does not store the correct mode. The ARMAsmBackend will emit nops for the last mode it knew about. In the example above, we still generate an arm nop if we add a `.code 32` to the end of the file. PR18019 llvm-svn: 195677
* ARM: diagnose invalid system LDM/STMTim Northover2013-11-121-0/+5
| | | | | | | | | | | | | The system LDM and STM instructions can't usually writeback to the base register. The one exception is when an LDM is actually an exception-return (i.e. contains PC in the register list). (There's already a test that "ldm sp!, {r0-r3, pc}^" works, which is why there is no positive test). rdar://problem/15223374 llvm-svn: 194512
* [ARM] Add support for MVFR2 which is new in ARMv8Artyom Skrobov2013-11-111-0/+5
| | | | llvm-svn: 194416
* [ARM] Handling for coprocessor instructions that are undefined starting from ↵Artyom Skrobov2013-11-081-2992/+16
| | | | | | ARMv8 (Thumb encodings) llvm-svn: 194263
* [ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 ↵Artyom Skrobov2013-11-084-26/+31
| | | | | | as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings llvm-svn: 194253
* ARM: permit bare dmb/dsb/isb aliases on Cortex-M0Tim Northover2013-11-051-1/+31
| | | | | | | | Cortex-M0 supports these 32-bit instructions despite being Thumb1 only (mostly). We knew about that but not that the aliases without the default "sy" operand were also permitted. llvm-svn: 194094
* Test cleanup for v8 instructionsBernard Ogden2013-10-293-7/+38
| | | | | | | Add some missing tests, factor out a test not specific to v8 into its own file. llvm-svn: 193611
* ARM: Add subtarget feature for CRCBernard Ogden2013-10-292-12/+26
| | | | | | | | Adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend. Differential Revision: http://llvm-reviews.chandlerc.com/D2036 llvm-svn: 193599
* Convert another llc -filetype=obj test.Rafael Espindola2013-10-281-0/+41
| | | | llvm-svn: 193539
* Return early from getUnconditionalBranchTargetOpValue if the branch target isLang Hames2013-10-281-2/+2
| | | | | | | | | | | | | | | | | an MCExpr, in order to avoid writing an encoded zero value in the immediate field. When getUnconditionalBranchTargetOpValue is called with an MCExpr target, we don't know what the final immediate field value should be. We shouldn't explicitly set the immediate field to an encoded zero value as zero is encoded with a non-zero bit pattern. This leads to bits being set that pollute the final immediate value. The nature of the encoding is such that the polluted bits only affect very large immediate values, explaining why this hasn't caused problems earlier. Fixes <rdar://problem/15155975>. llvm-svn: 193535
* [arm] Implement eabi_attribute, cpu, and fpu directives.Logan Chien2013-10-284-0/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | This commit allows the ARM integrated assembler to parse and assemble the code with .eabi_attribute, .cpu, and .fpu directives. To implement the feature, this commit moves the code from AttrEmitter to ARMTargetStreamers, and several new test cases related to cortex-m4, cortex-r5, and cortex-a15 are added. Besides, this commit also change the Subtarget->isFPOnlySP() to Subtarget->hasD16() to match the usage of .fpu directive. This commit changes the test cases: * Several .eabi_attribute directives in 2010-09-29-mc-asm-header-test.ll are removed because the .fpu directive already cover the functionality. * In the Cortex-A15 test case, the value for Tag_Advanced_SIMD_arch has be changed from 1 to 2, which is more precise. llvm-svn: 193524
* ARM: allow .thumb_func to be separated from symbol definitionTim Northover2013-10-251-1/+1
| | | | | | | | | | When assembling, a .thumb_func directive is supposed to be applicable to the next symbol definition, even if there are intervening directives. We were racing ahead to try and find it, and this commit should fix the issue. Patch by Gabor Ballabas llvm-svn: 193403
* ARM: tweak test to pass on all platformsTim Northover2013-10-251-1/+3
| | | | | | | A TableGen indeterminacy means that the reason for the failure can vary, and Windows gets the other option. llvm-svn: 193394
* ARM: Mark double-precision instructions as suchTim Northover2013-10-242-0/+200
| | | | | | | | | | | | This prevents us from silently accepting invalid instructions on (for example) Cortex-M4 with just single-precision VFP support. No tests for the extra Pat Requires because they're essentially assertions: the affected code should have been lowered to libcalls before ISel. rdar://problem/15302004 llvm-svn: 193354
* ARM: add a couple more NEON predicates.Tim Northover2013-10-241-1/+12
| | | | | | | | The fused multiply instructions were added in VFPv4 but are still NEON instructions, in particular they shouldn't be available on a Cortex-M4 not matter how floaty it is. llvm-svn: 193342
* ARM: mark various aliases with their architecture requirements.Tim Northover2013-10-242-0/+24
| | | | | | | | | | If an alias inherits directly from InstAlias then it doesn't get any default "Requires" values, so llvm-mc will allow it even on architectures that don't support the underlying instruction. This tidies up the obvious VFP and NEON cases I found. llvm-svn: 193340
* ARM: fix assert on unpredictable POP instruction.Tim Northover2013-10-242-5/+7
| | | | | | | | | | | POP instructions are aliased to the ARM LDM variants but have different syntax. This caused two problems: we tried to access a non-existent operand to annotate the '!', and the error message didn't make much sense. With some vigorous hand-waving in the error message both problems can be fixed. llvm-svn: 193322
* Make ARM hint ranges consistent, and add tests for these rangesArtyom Skrobov2013-10-234-2/+28
| | | | llvm-svn: 193238
* ARM: provide diagnostics on more writeback LDM/STM instructionsTim Northover2013-10-222-0/+23
| | | | | | | | | | | | | | The set of circumstances where the writeback register is allowed to be in the list of registers is rather baroque, but I think this implements them all on the assembly parsing side. For disassembly, we still warn about an ARM-mode LDM even if the architecture revision is < v7 (the required architecture information isn't available). It's a silly instruction anyway, so hopefully no-one will mind. rdar://problem/15223374 llvm-svn: 193185
* Add hint disassembly syntax for 16-bit Thumb hint instructions.Richard Barton2013-10-181-0/+17
| | | | | | Patch by Artyom Skrobov llvm-svn: 192972
* Add hardware division as a default feature on Cortex-A15. Also add test ↵Silviu Baranga2013-10-182-0/+61
| | | | | | cases to check this, and change diagnostics for the hwdiv-arm feature to something useful. llvm-svn: 192963
* Add subtarget feature support for Cortex-A53Bernard Ogden2013-10-142-2/+2
| | | | | | | Some previous implicit defaults have changed, for example FP and NEON are now on by default. llvm-svn: 192590
* [ARM] Fix FP ABI attributes with no VFP enabled.Amara Emerson2013-10-111-4/+4
| | | | llvm-svn: 192458
* [ARM] Improve build attributes emission.Amara Emerson2013-10-071-3/+4
| | | | llvm-svn: 192111
* ARM: allow cortex-m0 to use hint instructionsTim Northover2013-10-073-12/+37
| | | | | | | | | | | The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have been ported across to the v6M architecture. Fortunately, v6M seems to sit nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it fairly easily. rdar://problem/15144406 llvm-svn: 192097
* Remove some really nasty uses of hasRawTextSupport.Rafael Espindola2013-10-051-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When MC was first added, targets could use hasRawTextSupport to keep features working before they were added to the MC interface. The design goal of MC is to provide an uniform api for printing assembly and object files. Short of relaxations and other corner cases, a object file is just another representation of the assembly. It was never the intention that targets would keep doing things like if (hasRawTextSupport()) Set flags in one way. else Set flags in another way. When they do that they create two code paths and the object file is no longer just another representation of the assembly. This also then requires testing with llc -filetype=obj, which is extremelly brittle. This patch removes some of these hacks by replacing them with smaller ones. The ARM flag setting is trivial, so I just moved it to the constructor. For Mips, the patch adds two temporary hack directives that allow the assembly to represent the same things as the object file was already able to. The hope is that the mips developers will replace the hack directives with the same ones that gas uses and drop the -print-hack-directives flag. I will also try to implement a target streamer interface, so that we can move this out of the common code. In summary, for any new work, two rules of the thumb are * Don't use "llc -filetype=obj" in tests. * Don't add calls to hasRawTextSupport. llvm-svn: 192035
* [ARM] Warn on deprecated IT blocks in v8 AArch32 assembly.Amara Emerson2013-10-032-14/+9762
| | | | | | Patch by Artyom Skrobov. llvm-svn: 191885
* [ARM] Introduce the 'sevl' instruction in ARMv8.Joey Gouly2013-10-015-16/+22
| | | | | | | This also removes the restriction on the immediate field of the 'hint' instruction. llvm-svn: 191744
* [ARM] Fix Thumb(-2) diagnostic tests.Tilmann Scheller2013-09-302-12/+12
| | | | | | | | | Changing the diagnostic message for out of range branch targets in 191686 broke the tests. The diagnostic message for out of range branch targets was changed to be more consistent with the other diagnostics. llvm-svn: 191691
* [ARM] Use FileCheck instead of grep for ARM LDRD negative tests.Tilmann Scheller2013-09-301-19/+42
| | | | llvm-svn: 191683
* [ARM] Assembler: ARM LDRD with writeback requires the base register to be ↵Tilmann Scheller2013-09-301-0/+6
| | | | | | | | | | different from the destination registers. See ARM ARM A8.8.72. Violating this constraint results in unpredictable behavior. llvm-svn: 191678
* [ARM] Assembler: Add more negative tests for ARM LDRD.Tilmann Scheller2013-09-301-0/+8
| | | | llvm-svn: 191664
* ARM: Teach assembler to enforce constraints for ARM LDRD destination ↵Tilmann Scheller2013-09-272-20/+40
| | | | | | | | | | | | | | | | | | | register operands. As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints: LDRD<c> <Rt>, <Rt2>, ... (a) Rt must be even-numbered and not r14 (b) Rt2 must be R(t+1) If those two constraints are not met the result of executing the instruction will be unpredictable. Constraint (b) was already enforced, this commit adds support for constraint (a). Fixes rdar://14479793. llvm-svn: 191520
* ARM: Teach assembler to enforce constraint for Thumb2 LDRD ↵Tilmann Scheller2013-09-271-0/+9
| | | | | | | | | | | | | | | | | (literal/immediate) destination register operands. LDRD<c> <Rt>, <Rt2>, <label> LDRD<c> <Rt>, <Rt2>, [<Rn>{, #+/-<imm>}] LDRD<c> <Rt>, <Rt2>, [<Rn>], #+/-<imm> LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>]! As specified in A8.8.72/A8.8.73 in the ARM ARM, the T1 encoding has a constraint which enforces that Rt != Rt2. If this constraint is not met the result of executing the instruction will be unpredictable. Fixes rdar://14479780. llvm-svn: 191504
* [ARMv8] Add support for the v8 cryptography extensions.Amara Emerson2013-09-194-1/+173
| | | | llvm-svn: 190996
* 'svn add' the test cases.Joey Gouly2013-09-183-0/+62
| | | | llvm-svn: 190929
* [ARM] Fix the deprecation of MCR encodings that map to CP15{ISB,DSB,DMB}.Joey Gouly2013-09-171-3/+13
| | | | llvm-svn: 190862
* Fix tests for hasFPARMv8 name change (r190692)Amaury de la Vieuville2013-09-133-3/+3
| | | | | | Patch by Bradley Smith llvm-svn: 190694
* [ARMv8] Change hasV8Fp to hasFPARMv8, and other command line optionsJoey Gouly2013-09-131-1/+1
| | | | | | to be more consistent. llvm-svn: 190692
* Somehow this important part of the patch, where I actually check the Mask,Joey Gouly2013-09-121-3/+6
| | | | | | | | got lost during my iterations of review. Thanks to Hal for spotting it! llvm-svn: 190604
OpenPOWER on IntegriCloud