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* Tidy up a bit. Formatting only.Jim Grosbach2014-02-111-8/+8
| | | | llvm-svn: 201174
* ARM: Thumb2 LDR(literal) can target SP.Jim Grosbach2014-02-111-0/+5
| | | | | | | | | Fix a slightly overzealous destination register restriction for the 'without .w' alias. Add some explicit testcases. rdar://16033140 llvm-svn: 201173
* ARM: change attribute tests to use parsed formSaleem Abdulrasool2014-02-0828-525/+640
| | | | | | | | | This makes the tests more readable by using the -arm-attributes decoding support in llvm-readobj since that is now available. Change the invocation commands to be similar to other test and use a more precise triple (the tests only require ARM EABI support). llvm-svn: 201029
* Remove -arm-disable-ehabi optionRenato Golin2014-02-071-2/+12
| | | | llvm-svn: 200988
* ARM: Resolve thumb_bl fixup in same MCFragment.Logan Chien2014-02-051-0/+26
| | | | | | | | | | | | | | In Thumb1 mode, bl instruction might be selected for branches between basic blocks in the function if the offset is greater than 2KB. However, this might cause SEGV because the destination symbol is not marked as thumb function and the execution mode will be reset to ARM mode. Since we are sure that these symbols are in the same data fragment, we can simply resolve these local symbols, and don't emit any relocation information for this bl instruction. llvm-svn: 200842
* ARM IAS: support .object_archSaleem Abdulrasool2014-01-304-0/+78
| | | | | | | | | | The .object_arch directive indicates an alternative architecture to be specified in the object file. The directive does *not* effect the enabled feature bits for the object file generation. This is particularly useful when the code performs runtime detection and would like to indicate a lower architecture as the requirements than the actual instructions used. llvm-svn: 200451
* ARM IAS: support .movspSaleem Abdulrasool2014-01-302-0/+146
| | | | | | | | .movsp is an ARM unwinding directive that indicates to the unwinder that a register contains an offset from the current stack pointer. If the offset is unspecified, it defaults to zero. llvm-svn: 200449
* ARM: suuport .tlsdescseq directiveSaleem Abdulrasool2014-01-302-0/+68
| | | | | | | | | | | This enhances the ARMAsmParser to handle .tlsdescseq directives. This is a slightly special relocation. We must be able to generate them, but not consume them in assembly. The relocation is meant to assist the linker in generating a TLS descriptor sequence. The ELF target streamer is enhanced to append additional fixups into the current segment and that is used to emit the new R_ARM_TLS_DESCSEQ relocations. llvm-svn: 200448
* ARM: support TLS descriptor relocationsSaleem Abdulrasool2014-01-301-0/+6
| | | | | | | | Add support for tlsdesc relocations which are part of the ABI, marked as experimental. These relocations permit the linker to perform TLS reference optimizations. llvm-svn: 200447
* ARM: support tlscall relocationsSaleem Abdulrasool2014-01-301-0/+7
| | | | | | | | | | | | | | This adds support for TLS CALL relocations. TLS CALL relocations are used to indicate to the linker to generate appropriate entries to resolve TLS references via an appropriate function invocation (e.g. __tls_get_addr(PLT)). In order to accomodate the linker relaxation of the TLS access model for the references (GD/LD -> IE, IE -> LE), the relocation addend must be incomplete. This requires that the partial inplace value is also incomplete (i.e. 0). We simply avoid the offset value calculation at the time of the fixup adjustment in the ARM assembler backend. llvm-svn: 200446
* Enable EHABI by defaultRenato Golin2014-01-292-2/+6
| | | | | | | | | | | | | | | | | | | | | | After all hard work to implement the EHABI and with the test-suite passing, it's time to turn it on by default and allow users to disable it as a work-around while we fix the eventual bugs that show up. This commit also remove the -arm-enable-ehabi-descriptors, since we want the tables to be printed every time the EHABI is turned on for non-Darwin ARM targets. Although MCJIT EHABI is not working yet (needs linking with the right libraries), this commit also fixes some relocations on MCJIT regarding the EH tables/lib calls, and update some tests to avoid using EH tables when none are needed. The EH tests in the test-suite that were previously disabled on ARM now pass with these changes, so a follow-up commit on the test-suite will re-enable them. llvm-svn: 200388
* Tests for mode switchingDavid Woodhouse2014-01-281-0/+9
| | | | | | | 1. test that inlineasm works 2. test that relaxable instructions are re-encoded in the correct mode. llvm-svn: 200351
* ARM MC: Fix the initial DWARF CFI unwind info at the start of a functionMark Seaborn2014-01-271-0/+16
| | | | | | | | | | | | | | | | | | | | This brings MC into line with GNU 'as' on ARM, and it brings the ARM target into line with most other LLVM targets, which declare the initial CFI state with addInitialFrameState(). Without this, functions generated with .cfi_startproc/endproc on ARM will tend to cause GDB to abort with: gdb/dwarf2-frame.c:1132: internal-error: Unknown CFA rule. I've also tested this by comparing the output of "readelf -w" on the object files produced by llvm-mc and gas when given the .s file added here. This change is part of addressing PR18636. Differential Revision: http://llvm-reviews.chandlerc.com/D2597 llvm-svn: 200255
* MC: fix test locations/nameSaleem Abdulrasool2014-01-261-0/+13
| | | | | | | Placed the MC variant diagnostics in the wrong directory accidentally. Move them into their respective architecture specific directories. llvm-svn: 200161
* ARM: improve diagnostics for .word directiveSaleem Abdulrasool2014-01-261-0/+12
| | | | | | | | | If a complex expression was passed to the .word directive and the first part of the directive failed to parse, a secondary diagnostic would be produced that would clutter the error diagnostics. Improve the diagnostics by consuming the remainder of the statement. llvm-svn: 200160
* Reverting r199886 (Prevent repetitive warnings for unrecognized processors ↵Artyom Skrobov2014-01-251-15/+0
| | | | | | and features) llvm-svn: 200083
* Fix known typosAlp Toker2014-01-242-2/+2
| | | | | | | Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. llvm-svn: 200018
* Prevent repetitive warnings for unrecognized processors and featuresArtyom Skrobov2014-01-231-0/+15
| | | | llvm-svn: 199886
* tools: support decoding ARM EHABI opcodes in readobjSaleem Abdulrasool2014-01-211-18/+15
| | | | | | | | | | | | | | Add support to llvm-readobj to decode the actual opcodes. The ARM EHABI opcodes are a variable length instruction set that describe the operations required for properly unwinding stack frames. The primary motivation for this change is to ease the creation of tests for the ARM EHABI object emission as well as the unwinding directive handling in the ARM IAS. Thanks to Logan Chien for an extra test case! llvm-svn: 199708
* ARM IAS: add support for .unwind_raw directiveSaleem Abdulrasool2014-01-212-0/+186
| | | | | | | | | | | | This implements the unwind_raw directive for the ARM IAS. The unwind_raw directive takes the form of a stack offset value followed by one or more bytes representing the opcodes to be emitted. The opcode emitted will interpreted as if it were assembled by the opcode assembler via the standard unwinding directives. Thanks to Logan Chien for an extra test! llvm-svn: 199707
* ARM IAS: support .personalityindexSaleem Abdulrasool2014-01-212-0/+324
| | | | | | | | | | | | | The .personalityindex directive is equivalent to the .personality directive with the ARM EABI personality with the specific index (0, 1, 2). Both of these directives indicate personality routines, so enhance the personality directive handling to take into account personalityindex. Bonus fix: flush the UnwindContext at the beginning of a new function. Thanks to Logan Chien for additional tests! llvm-svn: 199706
* ARM: add tlsldo relocationKai Nacke2014-01-201-0/+5
| | | | | | | | | Add support for the symbol(tlsldo) relocation. This is required in order to solve PR18554. Reviewed by R. Golin, A. Korobeynikov. llvm-svn: 199644
* ARM ELF: ensure that the tag types are correctedSaleem Abdulrasool2014-01-191-0/+18
| | | | | | | | Ensure that the tag types are reflected on a replacement. This is particularly important for the compatibility tag which has multiple representations where the last definition wins. llvm-svn: 199577
* ARM: update build attributes for ABI r2.09Saleem Abdulrasool2014-01-191-2/+9
| | | | | | | Update names for the names as per the current ABI errata. Mark deprecated tags as such. llvm-svn: 199576
* ARM: Let the assembler reject v5 instructions in v4 mode.Benjamin Kramer2014-01-181-0/+8
| | | | | | PR18524. llvm-svn: 199559
* Add MLA alias for ARMv4 support.Renato Golin2014-01-172-0/+40
| | | | | | | | | | Fix MLA defs to use register class GPRnopc. Add encoding tests for multiply instructions. (Alias for MUL/SMLAL/UMLAL added by r199026.) Patch by Zhaoshi. llvm-svn: 199491
* Move the xscale build attribute test to the proper place and remove the old one.Amara Emerson2014-01-161-39/+0
| | | | | | The encoding of build attributes is already tested in CodeGen/ARM/build-attributes-encoding.s llvm-svn: 199393
* Fix parsing of .symver directive on ARMDavid Peixotto2014-01-152-0/+175
| | | | | | | | | | | | | | | ARM assembly syntax uses @ for a comment, execpt for the second parameter of the .symver directive which requires @ as part of the symbol name. This commit fixes the parsing of this directive by adding a special case for ARM for this one argumnet. To make the change we had to move the AllowAtInIdentifier variable to the MCAsmLexer interface (from AsmLexer) and expose a setter for the value. The ELFAsmParser then toggles this value when parsing the second argument to the .symver directive for a target that uses @ as a comment symbol llvm-svn: 199339
* ARM IAS: fix diagnostics of improper qualificationSaleem Abdulrasool2014-01-121-0/+15
| | | | | | | | An improper qualifier would result in a superfluous error due to the parser not consuming the remainder of the statement. Simply consume the remainder of the statement to avoid the error. llvm-svn: 199035
* ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructionsSaleem Abdulrasool2014-01-121-4/+4
| | | | | | | | | | | | | The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. llvm-svn: 199032
* TypoJoerg Sonnenberger2014-01-121-2/+1
| | | | llvm-svn: 199027
* Add missing mul aliases for armv4 support. Add checks that armv4 canJoerg Sonnenberger2014-01-121-1/+10
| | | | | | assemble the various mul instructions. llvm-svn: 199026
* ARM IAS: support emitting constant values in target expressionsSaleem Abdulrasool2014-01-111-0/+36
| | | | | | | | A 32-bit immediate value can be formed from a constant expression and loaded into a register. Add support to emit this into an object file. Because this value is a constant, a relocation must *not* be produced for it. llvm-svn: 199023
* Amending test/MC/ARM/thumb2-mclass.s to match its apparent original purpose ↵Artyom Skrobov2014-01-102-13/+47
| | | | | | (to test the ARMv6M/ARMv7M commonality), and creating a new test case for the differences between ARMv6M and ARMv7M llvm-svn: 198946
* Must not produce Tag_CPU_arch_profile for pre-ARMv7 cores (e.g. cortex-m0)Artyom Skrobov2014-01-101-3/+3
| | | | llvm-svn: 198945
* ARM IAS: support #:{lower,upper}16: for GNU compatibilitySaleem Abdulrasool2014-01-101-0/+44
| | | | | | | | The GNU assembler supports prefixing the expression with a '#' to indiciate that the value that is being moved is infact a constant. This improves the compatibility of the integrated assembler's parser for this. llvm-svn: 198916
* ARM IAS: support GNU extension for ldrd, strdSaleem Abdulrasool2014-01-101-0/+11
| | | | | | | | | The GNU assembler has an extension that allows for the elision of the paired register (dt2) for the LDRD and STRD mnemonics. Add support for this in the assembly parser. Canonicalise the usage during the instruction parsing from the specified version. llvm-svn: 198915
* ARM IAS: support implicit immediate 0s for {LD,ST}R{B,}TSaleem Abdulrasool2014-01-101-0/+8
| | | | | | | | | | | | | | | | The ARM ARM indicates the mnemonics as follows: ldrbt{<c>}{<q>} <Rt>, [<Rn>], {, #+/-<imm>} ldrt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>} strbt{<c>}{<q>} <Rt>, [<Rn>] {, #<imm>} strt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>} This improves the parser to deal with the implicit immediate 0 for the mnemonics as per the specification. Thanks to Joerg Sonnenberger for the tests! llvm-svn: 198914
* Fix a bug with the ARM thumb2 CBNZ and CBNZ instructions thatKevin Enderby2014-01-101-0/+33
| | | | | | | | | branch to the next instruction. This can not be encoded but can be turned into a NOP. rdar://15062072 llvm-svn: 198904
* ARM IAS: properly handle expression operandsSaleem Abdulrasool2014-01-081-0/+40
| | | | | | | Operands which involved label arithemetic would previously fail to parse. This corrects that by adding the additional case for the shift operand validation. llvm-svn: 198735
* Add ARM fconsts/fconstd aliases for vmov.f32/vmov.f64David Peixotto2014-01-073-0/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds the pre-UAL aliases of fconsts and fconstd for vmov.f32 and vmov.f64. They use an InstAlias rather than a MnemonicAlias to properly support the predicate operand. We need to support encoded 8-bit constants in order to implement the pre-UAL fconsts/fconstd aliases for vmov.f32/vmov.f64, so this commit also fixes parsing of encoded floating point constants used in vmov.f32/vmov.f64 instructions. Now we can support assembly code like this: fconsts s0, #0x70 which is equivalent to vmov.f32 s0, #1.0. Most of the code was already in place to support this feature. Previously the code was trying to accept encoded 8-bit float constants for the vmov.f32/vmov.f64 instructions. It looks like the support for parsing encoded floats was lost in a refactoring in commit r148556 and we did not have any tests in place to catch it. The change in this commit is to keep the parsed value as a 32-bit float instead of a 64-bit double because that is what the isFPImm() function expects to find. There is no loss of precision by using a 32-bit float here because we are still limited to an 8-bit encoded value in the end. Additionally, we explicitly reject encoded 8-bit floats for vmovf.32/64. This is the same as the current behavior, but we now do it explicitly rather than accidently. llvm-svn: 198697
* ARM IAS: allow more depth in contextual diagnosticsSaleem Abdulrasool2014-01-071-0/+30
| | | | | | | Switch the context to be SmallVectors. This allows for saving additional context when providing previous emission sites. llvm-svn: 198665
* ARM IAS: refactor unwind contextSaleem Abdulrasool2014-01-071-1/+1
| | | | | | | | Move the unwinding context for the ARM IAS into a helper class. This is purely a structural refactoring. A follow up change allows for recording additional depth to improve diagnostics. llvm-svn: 198664
* ARM IAS: improve .eabi_attribute handlingSaleem Abdulrasool2014-01-072-0/+127
| | | | | | | | Parse tag names as well as expressions. The former is part of the specification, the latter is for improved compatibility with the GNU assembler. Fix attribute value handling to be comformant to the specification. llvm-svn: 198662
* MCParser: introduce Note and use it for ARM AsmParserSaleem Abdulrasool2014-01-072-5/+5
| | | | | | | | Introduce a new virtual method Note into the AsmParser. This completements the existing Warning and Error methods. Use the new method to clean up the output of the unwind routines in the ARM AsmParser. llvm-svn: 198661
* [arm] Add softvfp to supported FPU names.Logan Chien2014-01-021-0/+8
| | | | llvm-svn: 198313
* ARM IAS: account for predicated pre-UAL mnemonicsSaleem Abdulrasool2013-12-302-0/+26
| | | | | | | | Checking the trailing letter of the mnemonic is insufficient. Be more thorough in the scanning of the instruction to ensure that we correctly work with the predicated mnemonics. llvm-svn: 198235
* ARM: provide VFP aliases for pre-V6 mnemonicsSaleem Abdulrasool2013-12-292-0/+150
| | | | | | | In order to provide compatibility with the GNU assembler, provide aliases for pre-UAL mnemonics for floating point operations. llvm-svn: 198172
* Recognize armv7a and friends as aliases for armv7-a etc. for the purposeJoerg Sonnenberger2013-12-264-0/+121
| | | | | | of architecture naming. llvm-svn: 198043
* ARM IAS: support .even directiveSaleem Abdulrasool2013-12-261-0/+70
| | | | | | | The .even directive aligns content to an evan-numbered address. This is an ARM specific directive applicable to any section. llvm-svn: 198031
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