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* ARM: Fix another regression introduced in r223113Asiri Rathnayake2015-02-121-0/+2
| | | | | | | | | | | | | | | | | | | | | The changes in r223113 (ARM modified-immediate syntax) have broken instructions like: mov r0, #~0xffffff00 The problem is that I've added a spurious range check on the immediate operand to ensure that it lies between INT32_MIN and UINT32_MAX. While this range check is correct in theory, it causes problems because the operand is stored in an int64_t (by MC). So valid 32-bit constants like \#~0xffffff00 become out of range. The solution is to simply remove this range check. It is not possible to validate the range of the immediate operand with the current setup because: 1) The operand is stored in an int64_t by MC, 2) The immediate can be of the forms #imm, #-imm, #~imm or even #((~imm)) etc. So we just chop the value to 32 bits and use it. Also noted that the original range check was note tested by any of the unit tests. I've added a new test to cover #~imm kind of operands. Change-Id: I411e90d84312a2eff01b732bb238af536c4a7599 llvm-svn: 228920
* [ARM] Add armv6s[-]m as an alias to armv6[-]mBradley Smith2015-02-101-0/+3
| | | | llvm-svn: 228696
* [ARM] Fix subtarget feature set truncation when using .cpu directiveBradley Smith2015-02-041-0/+4
| | | | | | | This is a bug that was caused due to storing the feature bitset in a 32-bit variable when it is a 64-bit mask, discarding the top half of the feature set. llvm-svn: 228151
* Fix some unnoticed/unwanted behavior change from r222319.Frederic Riss2015-02-041-0/+3
| | | | | | | | | The ARM assembler allows register alias redefinitions as long as it targets the same register. r222319 broke that. In the AArch64 case it would just produce a new warning, but in the ARM case it would error out on previously accepted assembler. llvm-svn: 228109
* ARM: further correct .fpu directive handlingSaleem Abdulrasool2015-01-301-0/+37
| | | | | | | | | | If the original FPU specification involved a restricted VFP unit (d16), ensure that we reset the functionality when we encounter a new FPU type. In particular, if the user specified vfpv3-d16, but switched to a VFPv3 (which has 32 double precision registers), we would fail to reset the D16 feature, and treat it as being equivalent to vfpv3-d16. llvm-svn: 227603
* ARM: improve caret diagnostics for invalid FPU nameSaleem Abdulrasool2015-01-301-0/+10
| | | | | | | In the case of an invalid FPU name, place the caret at the name rather than FPU directive. llvm-svn: 227595
* ARM: correct handling of .fpu directiveSaleem Abdulrasool2015-01-301-0/+63
| | | | | | | | | | | | | The FPU directive permits the user to switch the target FPU, enabling instructions that would be otherwise unavailable. However, when configuring the new subtarget features, we would not enable the implied functions for newer FPUs. This would result in invalid rejection of valid input. Ensure that we inherit the implied FPU functionality when enabling newer versions of the FPU. Fortunately, these are mostly hierarchical, unlike the CPUs. Addresses PR22395. llvm-svn: 227584
* ARM: fail less catastrophically on invalid Windows inputSaleem Abdulrasool2015-01-221-0/+14
| | | | | | | | | | | | Windows supports a restricted set of relocations (compared to ARM ELF). In some cases, we may end up generating an unsupported relocation. This can occur with bad input to the assembler in particular (the frontend should never generate code that cannot be compiled). Generate an error rather than just aborting. The change in the API is driven by the desire to provide a slightly more helpful message for debugging purposes. llvm-svn: 226779
* [ARM] SSAT/USAT with an 'asr #32' shift should result in an undefined ↵Bradley Smith2015-01-191-1/+4
| | | | | | encoding rather than unpredictable llvm-svn: 226469
* [ARM] Fixup sign extend instruction availability w.r.t. DSP extensionBradley Smith2015-01-191-0/+24
| | | | llvm-svn: 226468
* IR: Move MDLocation into placeDuncan P. N. Exon Smith2015-01-141-1/+1
| | | | | | | | | | | | | | | | | | | | This commit moves `MDLocation`, finishing off PR21433. There's an accompanying clang commit for frontend testcases. I'll attach the testcase upgrade script I used to PR21433 to help out-of-tree frontends/backends. This changes the schema for `DebugLoc` and `DILocation` from: !{i32 3, i32 7, !7, !8} to: !MDLocation(line: 3, column: 7, scope: !7, inlinedAt: !8) Note that empty fields (line/column: 0 and inlinedAt: null) don't get printed by the assembly writer. llvm-svn: 226048
* Correct POP handling for v7mJyoti Allur2015-01-141-5/+11
| | | | llvm-svn: 225972
* ARM: add support for segment base relocations (SBREL)Saleem Abdulrasool2015-01-112-0/+37
| | | | | | | | This adds support for parsing and emitting the SBREL relocation variant for the ARM target. Handling this relocation variant is necessary for supporting the full ARM ELF specification. Addresses PR22128. llvm-svn: 225595
* tests: fix previous commitSaleem Abdulrasool2015-01-101-10/+6
| | | | | | | The previous commit accidentally missed changes to the test output checking, resulting in an errant failure. llvm-svn: 225577
* test: merge ARM relocations testSaleem Abdulrasool2015-01-102-17/+15
| | | | | | | | There is a fair number of relocations that are part of the AAELF specification. Simply merge the tests into a single test file, otherwise, we will end up with far too many test files to test each relocation type. NFC. llvm-svn: 225576
* tests: convert a couple of ARM relocation tests to readobjSaleem Abdulrasool2015-01-102-8/+16
| | | | | | | These tests are checking the relocation generation. Use the readobj output as it is much easier to follow when glancing over the tests. llvm-svn: 225575
* ARM: add support for R_ARM_ABS16Saleem Abdulrasool2015-01-091-0/+13
| | | | | | Add support for R_ARM_ABS16 relocation mapping. Addresses PR22156. llvm-svn: 225510
* test: add additional test for SVN r225507Saleem Abdulrasool2015-01-091-0/+2
| | | | | | | Add an additional test case to ensure that we generate the relocation even if the thumb target is used. llvm-svn: 225509
* ARM: add support for R_ARM_ABS8 relocationsSaleem Abdulrasool2015-01-091-0/+10
| | | | | | Add support for R_ARM_ABS8 relocation. Addresses PR22126. llvm-svn: 225507
* Parse Tag_compatibility correctly.Charlie Turner2015-01-053-4/+5
| | | | | | | | Tag_compatibility takes two arguments, but before this patch it would erroneously accept just one, it now produces an error in that case. Change-Id: I530f918587620d0d5dfebf639944d6083871ef7d llvm-svn: 225167
* Emit the build attribute Tag_conformance.Charlie Turner2015-01-051-5/+8
| | | | | | | | | | | Claim conformance to version 2.09 of the ARM ABI. This build attribute must be emitted first amongst the build attributes when written to an object file. This is to simplify conformance detection by consumers. Change-Id: If9eddcfc416bc9ad6e5cc8cdcb05d0031af7657e llvm-svn: 225166
* ARM: further improve deprecated diagnosis (LDM)Saleem Abdulrasool2014-12-201-5/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM ARM states: LDM/LDMIA/LDMFD: The SP can be in the list. However, ARM deprecates using these instructions with SP in the list. ARM deprecates using these instructions with both the LR and the PC in the list. LDMDA/LDMFA/LDMDB/LDMEA/LDMIB/LDMED: The SP can be in the list. However, instructions that include the SP in the list are deprecated. Instructions that include both the LR and the PC in the list are deprecated. POP: The SP can only be in the list before ARMv7. ARM deprecates any use of ARM instructions that include the SP, and the value of the SP after such an instruction is UNKNOWN. ARM deprecates the use of this instruction with both the LR and the PC in the list. Attempt to diagnose use of deprecated forms of these instructions. This mirrors the previous changes to diagnose use of the deprecated forms of STM in ARM mode. llvm-svn: 224682
* ARM: fix an off-by-one in the register list accessSaleem Abdulrasool2014-12-181-5/+13
| | | | | | | | | Fix an off-by-one access introduced in 224502 for push.w and pop.w with single register operands. Add test cases for both scenarios. Thanks to Asiri Rathnayake for pointing out the failure! llvm-svn: 224521
* ARM: improve instruction validation for thumb modeSaleem Abdulrasool2014-12-183-14/+101
| | | | | | | | | | | | | | | | | | | | | | | | | The ARM Architecture Reference Manual states the following: LDM{,IA,DB}: The SP cannot be in the list. The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. POP: The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. PUSH: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. STM:{,IA,DB}: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. llvm-svn: 224502
* test: avoid unnecessary temporary filesSaleem Abdulrasool2014-12-181-8/+8
| | | | | | Use pipes and redirect the error output to FileCheck directly. NFC. llvm-svn: 224501
* ARM: correct an off-by-one in an assertSaleem Abdulrasool2014-12-171-0/+6
| | | | | | | | The assert was off-by-one, resulting in failures for valid input. Thanks to Asiri Rathnayake for pointing out the failure! llvm-svn: 224432
* ARM: diagnose deprecated syntaxSaleem Abdulrasool2014-12-161-0/+147
| | | | | | | | | | | | | The use of SP and PC in the register list for stores is deprecated on ARM (ARM ARM A.8.8.199): ARM deprecates the use of ARM instructions that include the SP or the PC in the list. Provide a deprecation warning from the assembler in the case that the syntax is ever seen. llvm-svn: 224319
* IR: Make metadata typeless in assemblyDuncan P. N. Exon Smith2014-12-151-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that `Metadata` is typeless, reflect that in the assembly. These are the matching assembly changes for the metadata/value split in r223802. - Only use the `metadata` type when referencing metadata from a call intrinsic -- i.e., only when it's used as a `Value`. - Stop pretending that `ValueAsMetadata` is wrapped in an `MDNode` when referencing it from call intrinsics. So, assembly like this: define @foo(i32 %v) { call void @llvm.foo(metadata !{i32 %v}, metadata !0) call void @llvm.foo(metadata !{i32 7}, metadata !0) call void @llvm.foo(metadata !1, metadata !0) call void @llvm.foo(metadata !3, metadata !0) call void @llvm.foo(metadata !{metadata !3}, metadata !0) ret void, !bar !2 } !0 = metadata !{metadata !2} !1 = metadata !{i32* @global} !2 = metadata !{metadata !3} !3 = metadata !{} turns into this: define @foo(i32 %v) { call void @llvm.foo(metadata i32 %v, metadata !0) call void @llvm.foo(metadata i32 7, metadata !0) call void @llvm.foo(metadata i32* @global, metadata !0) call void @llvm.foo(metadata !3, metadata !0) call void @llvm.foo(metadata !{!3}, metadata !0) ret void, !bar !2 } !0 = !{!2} !1 = !{i32* @global} !2 = !{!3} !3 = !{} I wrote an upgrade script that handled almost all of the tests in llvm and many of the tests in cfe (even handling many `CHECK` lines). I've attached it (or will attach it in a moment if you're speedy) to PR21532 to help everyone update their out-of-tree testcases. This is part of PR21532. llvm-svn: 224257
* Fix modified immediate bug reported by MC Hammer.Asiri Rathnayake2014-12-091-4/+7
| | | | | | | | | | | | | Instructions of the form [ADD Rd, pc, #imm] are manually aliased in processInstruction() to use ADR. To accomodate this, mod_imm handling had to be tweaked a bit. Turns out it was the manual aliasing that must be tweaked to accommodate mod_imms instead. More information about the parsed instruction is available at the point where processInstruction() is invoked, which makes it easier to detect a mod_imm at that point rather than trying to detect a potential alias when a mod_imm is being prepped. Added a test case and fixed some white spaces as well. llvm-svn: 223772
* Improvements to ARM assembler testsAsiri Rathnayake2014-12-051-70/+445
| | | | | | | | | | | | | | | | | | | | | | | | No functional changes. Got myself bitten in r223113 when adding support for modified immediate syntax (regressions reported by joerg@britannica.bec.de, fixes in r223366 and r223381). Our assembler tests did not cover serveral different syntax variants. This patch expands the test coverage to check for the following cases: 1. Modified immediate operands may be expressed with expressions, as in #(4 * 2) instead of #8. 2. Modified immediate operands may be _optionally_ prefixed by a '#' symbol or a '$' symbol. 3. Certain instructions (e.g. ADD) support single input register variants; [ADD r0, #mod_imm] is same as [ADD r0, r0, #mod_imm]. 4. Certain instructions have aliases which convert plain immediates to modified immediates. For an example, [ADD r0, -10] is not valid because -10 (in two's complement) cannot be encoded as a modified immediate, but ARMInstrInfo.td defines an alias which can transform this into a [SUB r0, 10]. llvm-svn: 223475
* Fix yet another unseen regression caused by r223113Asiri Rathnayake2014-12-042-1/+7
| | | | | | | | | | r223113 added support for ARM modified immediate assembly syntax. Which assumes all immediate operands are prefixed with a '#'. This assumption is wrong as per the ARMARM - which recommends that all '#' characters be treated optional. The current patch fixes this regression and adds a test case. A follow-up patch will expand the test coverage to other instructions. llvm-svn: 223381
* Fix a minor regression introduced in r223113Asiri Rathnayake2014-12-041-0/+42
| | | | | | | | | | r223113 added support for ARM modified immediate assembly syntax. That patch has broken support for immediate expressions, as in: add r0, #(4 * 4) It wasn't caught because we don't have any tests for this feature. This patch fixes this regression and adds test cases. llvm-svn: 223366
* Revert "[Thumb/Thumb2] Added restrictions on PC, LR, SP in the register list ↵Rafael Espindola2014-12-043-38/+7
| | | | | | | | | | for PUSH/POP/LDM/STM. <Differential Revision: http://reviews.llvm.org/D6090>" This reverts commit r223356. It was failing check-all (MC/ARM/thumb.s in particular). llvm-svn: 223363
* [Thumb/Thumb2] Added restrictions on PC, LR, SP in the register list for ↵Jyoti Allur2014-12-043-7/+38
| | | | | | PUSH/POP/LDM/STM. <Differential Revision: http://reviews.llvm.org/D6090> llvm-svn: 223356
* Introduce CPUStringIsValid() into MCSubtargetInfo and use it for ARM .cpu ↵Roman Divacky2014-12-021-0/+13
| | | | | | | | | | parsing. Previously .cpu directive in ARM assembler didnt switch to the new CPU and therefore acted as a nop. This implemented real action for .cpu and eg. allows to assembler FreeBSD kernel with -integrated-as. llvm-svn: 223147
* Add support for ARM modified-immediate assembly syntax.Asiri Rathnayake2014-12-023-4/+236
| | | | | | | | | | | | | | | | | | | | Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
* Add Thumb HVC and ERET virtualisation extension instructions.Charlie Turner2014-12-011-0/+59
| | | | | | | Patch by Matthew Wahab. Change-Id: I131f71c1150d5fa797066a18e09d526c19bf9016 llvm-svn: 222990
* Add ARM ERET and HVC virtualisation extension instructions.Charlie Turner2014-12-011-0/+42
| | | | | | | Patch by Matthew Wahab. Change-Id: Iad75f078fbaa4ecc7d7a4820ad9b3930679cbbbb llvm-svn: 222989
* Fix wrong encoding of MRSBanked.Charlie Turner2014-11-281-33/+33
| | | | | | | Patch by Matthew Wahab. Change-Id: Ia2a001ca2760028ea360fe77b56f203a219eefbc llvm-svn: 222920
* Stop uppercasing build attribute data.Charlie Turner2014-11-275-10/+9
| | | | | | | | | | | | | | | | | | | | | | | | The string data for string-valued build attributes were being unconditionally uppercased. There is no mention in the ARM ABI addenda about case conventions, so it's technically implementation defined as to whether the data are capitialised in some way or not. However, there are good reasons not to captialise the data. * It's less work. * Some vendors may legitimately have case-sensitive checks for these attributes which would fail on LLVM generated object files. * There could be locale issues with uppercasing. The original reasons for uppercasing appear to have stemmed from an old codesourcery toolchain behaviour, see http://comments.gmane.org/gmane.comp.compilers.llvm.cvs/87133 This patch makes the object file emitted no longer captialise string data, it encodes as seen in the assembly source. Change-Id: Ibe20dd6e60d2773d57ff72a78470839033aa5538 llvm-svn: 222882
* Fix transformation of add with pc argument to adr for non-immediateJoerg Sonnenberger2014-11-211-2/+8
| | | | | | arguments. llvm-svn: 222587
* [ELF] Prevent ARM ELF object writer from generating deprecated relocation ↵Jyoti Allur2014-11-201-2/+2
| | | | | | code R_ARM_PLT32 llvm-svn: 222414
* Fix bashism in tests added by r221341Oliver Stannard2014-11-051-2/+2
| | | | llvm-svn: 221342
* [ARM] Honor FeatureD16 in the assembler and disassemblerOliver Stannard2014-11-053-7/+31
| | | | | | | | | | | | | | | Some ARM FPUs only have 16 double-precision registers, rather than the normal 32. LLVM represents this with the D16 target feature. This is currently used by CodeGen to avoid using high registers when they are not available, but the assembler and disassembler do not. I fix this in the assmebler and disassembler rather than the InstrInfo.td files, as the latter would require a large number of changes everywhere one of the floating-point instructions is referenced in the backend. This solution is similar to the one used for co-processor numbers and MSR masks. llvm-svn: 221341
* Add missing tests for build attribute encodings in object files.Charlie Turner2014-11-041-17/+106
| | | | | | | | | test/MC/ARM/directive-eabi_attribute.s was missing several tests of object file encodings relative to the existing tests for assembly file encodings. This commit adds the missing tests. Change-Id: Ie110ca02b65e8f4d4c77f437bd09d03607fa5c0d llvm-svn: 221250
* Remove the cortex-a9-mp CPU.Charlie Turner2014-11-031-1/+1
| | | | | | | | | | | | | | | | | | This CPU definition is redundant. The Cortex-A9 is defined as supporting multiprocessing extensions. Remove its definition and update appropriate tests. LLVM defines both a cortex-a9 CPU and a cortex-a9-mp CPU. The only difference between the two CPU definitions in ARM.td is that cortex-a9-mp contains the feature FeatureMP for multiprocessing extensions. This is redundant since the Cortex-A9 is defined as having multiprocessing extensions in the TRMs. armcc also defines the Cortex-A9 as having multiprocessing extensions by default. Change-Id: Ifcadaa6c322be0a33d9d2a39cfdd7da1d75981a7 llvm-svn: 221166
* Merge the directive-eabi_attribute.s and directive-eabi_attribute-2.s tests.Charlie Turner2014-11-032-142/+146
| | | | | | | | | | | | | test/MC/ARM/directive-eabi_attribute.s had gotten out-of-sync with test/MC/ARM/directive-eabi_attribute-2.s. The former tests the encoding of build attributes in object files, and the latter the encoding in assembly files. Since both these tests need to be updated at the same time, it makes sense to combine them into a single test. The object file encodings are being checked against the ouput of -arm-attributes rather than by direct byte comparisons which makes for easier reading. Change-Id: I0075de506ae5626fb2fa235383fe5ce6a65a15a9 llvm-svn: 221155
* Update test/MC/ARM/coff-debugging-secrel.ll expectations to fix breakage ↵Timur Iskhodzhanov2014-10-241-2/+4
| | | | | | caused by r220544 llvm-svn: 220548
* [dwarfdump] Dump DW_AT_ranges values inline in the debug_info dump.Frederic Riss2014-10-231-1/+1
| | | | | | | | | | | The output looks like that: DW_AT_ranges [FORM_data4] (0x00000000 [0x00000001000024a0 - 0x00000001000024c2) [0x0000000100002505 - 0x000000010000268b)) Differential Revision: http://reviews.llvm.org/D5712 llvm-svn: 220466
* [Thumb/Thumb2] Implement restrictions on SP in register list on LDM, STM ↵Jyoti Allur2014-10-221-0/+46
| | | | | | variants in thumb mode llvm-svn: 220379
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