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* [ARM] Add diag string for movw/movt immediates in assemblyOliver Stannard2017-10-042-2/+6
| | | | | | | | | This adds diagnostics for invalid immediate operands to the MOVW and MOVT instructions (ARM and Thumb). Differential revision: https://reviews.llvm.org/D31879 llvm-svn: 314888
* [ARM, Asm] Change grammar of immediate operand diagnosticsOliver Stannard2017-10-0412-63/+63
| | | | | | | | | | | | | | | | | Currently, our diagnostics for assembly operands are not consistent. Some start with (for example) "immediate operand must be ...", and some with "operand must be an immediate ...". I think the latter form is preferable for a few reasons: * It's unambiguous that it is referring to the expected type of operand, not the type the user provided. For example, the user could provide an register operand, and get a message taking about an operand is if it is already an immediate, just not in the accepted range. * It allows us to have a consistent style once we add diagnostics for operands that could take two forms, for example a label or pc-relative memory operand. Differential revision: https://reviews.llvm.org/D36689 llvm-svn: 314887
* [ARM] Use table-gen'd assembly operand diags in ARM asm parserOliver Stannard2017-10-032-3/+3
| | | | | | | | | | | | This switches the ARM AsmParser to use assembly operand diagnostics from tablegen, rather than a switch statement on the ARMMatchResultTy. It moves the existing diagnostic strings to tablegen, but adds no new ones, so this is NFC except for one diagnostic string that had an off-by-1 error in the hand-written switch statement. Differential revision: https://reviews.llvm.org/D31607 llvm-svn: 314804
* [ARM, Asm] Use correct source location for register tokensOliver Stannard2017-10-031-0/+12
| | | | | | | | | | | | tryParseRegister advances the lexer, so we need to take copies of the start and end locations of the register operand before calling it. Previously, the caret in the diagnostic pointer to the comma after the r0 operand in the test, rather than the start of the operand. Differential revision: https://reviews.llvm.org/D31537 llvm-svn: 314799
* [ARM] Use new assembler diags for ARMOliver Stannard2017-10-0341-2001/+2176
| | | | | | | | | | | | | | | This converts the ARM AsmParser to use the new assembly matcher error reporting mechanism, which allows errors to be reported for multiple instruction encodings when it is ambiguous which one the user intended to use. By itself this doesn't improve many error messages, because we don't have diagnostic text for most operand types, but as we add that then this will allow more of those diagnostic strings to be used when they are relevant. Differential revision: https://reviews.llvm.org/D31530 llvm-svn: 314779
* [ARM] v8.3-a complex number supportSam Parker2017-09-291-0/+180
| | | | | | | | | | | | | | | New instructions are added to AArch32 and AArch64 to aid floating-point multiplication and addition of complex numbers, where the complex numbers are packed in a vector register as a pair of elements. The Imaginary part of the number is placed in the more significant element, and the Real part of the number is placed in the less significant element. This patch adds assembler for the ARM target. Differential Revision: https://reviews.llvm.org/D36789 llvm-svn: 314511
* [ARM] Fix assembly and disassembly for VMRS/VMSRAndre Vieira2017-09-221-0/+180
| | | | | | | Reviewed by: t.p.northover Differential Revision: https://reviews.llvm.org/D36306 llvm-svn: 313979
* [dwarfdump] Add verbose output for .debug-line sectionJonas Devlieghere2017-09-214-23/+26
| | | | | | | | | | | | This patch adds dumping of line table instructions as well as the final state at each specified pc value in verbose mode. This is essentially the same as the default in Darwin's dwarfdump. Dumping the actual line table opcodes can be particularly useful for something like debugging a bad `.debug_line` section. Differential revision: https://reviews.llvm.org/D37971 llvm-svn: 313910
* [ARM] Relax 'cpsie'/'cpsid' flag parsing.Jonathan Roelofs2017-09-191-0/+2
| | | | | | | | | | The ARM docs suggest in examples that the flags can have either case, and there are applications in the wild that (libopencm3, for example) that expect to be able to use the uppercase spelling. https://reviews.llvm.org/D37953 llvm-svn: 313680
* [ARM] Fix for indexed dot product instruction descriptionsSjoerd Meijer2017-09-181-0/+22
| | | | | | | | | | | The indexed dot product instructions only accept the lower 16 D-registers as the indexed register, but we were e.g. incorrectly accepting: vudot.u8 d16,d16,d18[0] Differential Revision: https://reviews.llvm.org/D37968 llvm-svn: 313531
* llvm-dwarfdump: automatically dump both regular and .dwo variant of sectionsAdrian Prantl2017-09-134-19/+8
| | | | | | | | | | | | Since users typically don't really care about the .dwo / non.dwo distinction, this patch makes it so dwarfdump --debug-<info,...> dumps .debug_info and (if available) also .debug_info.dwo. This simplifies the command line interface (I've removed all dwo-specific dump options) and makes the tool friendlier to use. Differential Revision: https://reviews.llvm.org/D37771 llvm-svn: 313207
* llvm-dwarfdump: Make -brief the default and add a -verbose option instead.Adrian Prantl2017-09-116-9/+9
| | | | | | Differential Revision: https://reviews.llvm.org/D37717 llvm-svn: 312972
* [ARM] Enable the use of SVC anywhere in an IT blockAndre Vieira2017-09-111-0/+6
| | | | | | Differential Revision: https://reviews.llvm.org/D37374 llvm-svn: 312908
* [ARM] Add 2-operand assembly aliases for Thumb1 ADD/SUBOliver Stannard2017-09-012-3/+73
| | | | | | | | | | | | | | | | This adds 2-operand assembly aliases for these instructions: add r0, r1 => add r0, r0, r1 sub r0, r1 => sub r0, r0, r1 Previously this syntax was only accepted for Thumb2 targets, where the wide versions of the instructions were used. This patch allows the 2-operand syntax to be used for Thumb1 targets, and selects the narrow encoding when it is used for Thumb2 targets. Differential revision: https://reviews.llvm.org/D37377 llvm-svn: 312321
* ARM: use internal relocations for local symbols after all.Tim Northover2017-08-231-0/+18
| | | | | | | | | | | Switching to external relocations for ARM-mode branches (to allow Thumb interworking when the offset is unencodable) causes calls to temporary symbols to be miscompiled and instead go to the parent externally visible symbol. Calling a temporary never happens in compiled code, but can occasionally in hand-written assembly. llvm-svn: 311611
* [ARM][AArch64] v8.3-A Javascript ConversionSam Parker2017-08-221-0/+16
| | | | | | | | | | Armv8.3-A adds instructions that convert a double-precision floating point number to a signed 32-bit integer with round towards zero, designed for improving Javascript performance. Differential Revision: https://reviews.llvm.org/D36785 llvm-svn: 311448
* [AsmParser] Recommit: Hash is not a comment on some targetsOliver Stannard2017-08-211-33/+33
| | | | | | | | | | | | | | | Re-committing after r311325 fixed an unintentional use of '#' comments in clang. The '#' token is not a comment for all targets (on ARM and AArch64 it marks an immediate operand), so we shouldn't treat it as such. Comments are already converted to AsmToken::EndOfStatement by AsmLexer::LexLineComment, so this check was unnecessary. Differential Revision: https://reviews.llvm.org/D36405 llvm-svn: 311326
* [ARM][AArch64] Cortex-A75 and Cortex-A55 supportSam Parker2017-08-212-0/+4
| | | | | | | | | | | | | | | | | | This patch introduces support for Cortex-A75 and Cortex-A55, Arm's latest big.LITTLE A-class cores. They implement the ARMv8.2-A architecture, including the cryptography and RAS extensions, plus the optional dot product extension. They also implement the RCpc AArch64 extension from ARMv8.3-A. Cortex-A75: https://developer.arm.com/products/processors/cortex-a/cortex-a75 Cortex-A55: https://developer.arm.com/products/processors/cortex-a/cortex-a55 Differential Revision: https://reviews.llvm.org/D36667 llvm-svn: 311316
* ARM: use an external relocation for calls from MachO ARM mode.Tim Northover2017-08-181-4/+4
| | | | | | | The internal (__text-relative) relocation risks the offset not being encodable if the destination is Thumb. llvm-svn: 311187
* [ARM] Assembler support for the ARMv8.2a dot product instructionsSjoerd Meijer2017-08-113-0/+89
| | | | | | | | | Commit r310480 added the AArch64 ARMv8.2a dot product instructions; this adds the AArch32 instructions. Differential Revision: https://reviews.llvm.org/D36575 llvm-svn: 310701
* Revert "[AsmParser] Hash is not a comment on some targets"Ahmed Bougacha2017-08-101-33/+33
| | | | | | | | This reverts commit r310457. It causes clang-produced IR to fail llvm codegen. llvm-svn: 310662
* [AsmParser] Hash is not a comment on some targetsOliver Stannard2017-08-091-33/+33
| | | | | | | | | | | | The '#' token is not a comment for all targets (on ARM and AArch64 it marks an immediate operand), so we shouldn't treat it as such. Comments are already converted to AsmToken::EndOfStatement by AsmLexer::LexLineComment, so this check was unnecessary. Differential Revision: https://reviews.llvm.org/D36405 llvm-svn: 310457
* Revert "[ARM] Fix assembly and disassembly for VMRS/VMSR"Tim Northover2017-08-083-180/+20
| | | | | | | | This reverts r310243. Only MVFR2 is actually restricted to v8 and it'll be a little while before we can get a proper fix together. Better that we allow incorrect code than reject correct in the meantime. llvm-svn: 310384
* [ARM] Fix assembly and disassembly for VMRS/VMSRAndre Vieira2017-08-073-20/+180
| | | | | | | | | | | | | | | | This patch addresses two issues with assembly and disassembly for VMRS/VMSR: 1.currently VMRS/VMSR instructions accessing fpsid, mvfr{0-2} and fpexc, are accepted for non ARMv8-A targets. 2. all VMRS/VMSR instructions accept writing/reading to PC and SP, when only ARMv7-A and ARMv8-A should be allowed to write/read to SP and none to PC. This patch addresses those issues and adds tests for these cases. Differential Revision: https://reviews.llvm.org/D36306 llvm-svn: 310243
* [ARM] Unify handling of M-Class system registersJaved Absar2017-07-191-7/+2
| | | | | | | | | | | | | | | | This patch cleans up and fixes issues in the M-Class system register handling: 1. It defines the system registers and the encoding (SYSm values) in one place: a new ARMSystemRegister.td using SearchableTable, thereby removing the hand-coded values which existed in multiple places. 2. Some system registers e.g. BASEPRI_MAX_NS which do not exist were being allowed! Ref: ARMv6/7/8M architecture reference manual. Reviewed by: @t.p.northover, @olist01, @john.brawn Differential Revision: https://reviews.llvm.org/D35209 llvm-svn: 308456
* fix typos in comments; NFCHiroshi Inoue2017-07-161-1/+1
| | | | llvm-svn: 308126
* Add back a CHECK line.Rafael Espindola2017-07-121-0/+1
| | | | | | | | I accidentally removed it in r307730. Thanks to Martin Storsjö for noticing! llvm-svn: 307801
* Fully fix the movw/movt addend.Rafael Espindola2017-07-111-1/+12
| | | | | | | | | | The issue is not if the value is pcrel. It is whether we have a relocation or not. If we have a relocation, the static linker will select the upper bits. If we don't have a relocation, we have to do it. llvm-svn: 307730
* [ARM, ELF] Don't shift movt relocation offsetsMartin Storsjo2017-07-111-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For ELF, a movw+movt pair is handled as two separate relocations. If an offset should be applied to the symbol address, this offset is stored as an immediate in the instruction (as opposed to stored as an offset in the relocation itself). Even though the actual value stored in the movt immediate after linking is the top half of the value, we need to store the unshifted offset prior to linking. When the relocation is made during linking, the offset gets added to the target symbol value, and the upper half of the value is stored in the instruction. This makes sure that movw+movt with offset symbols get properly handled, in case the offset addition in the lower half should be carried over to the upper half. This makes the output from the additions to the test case match the output from GNU binutils. For COFF and MachO, the movw/movt relocations are handled as a pair, and the overflow from the lower half gets carried over to the movt, so they should keep the shifted offset just as before. Differential Revision: https://reviews.llvm.org/D35242 llvm-svn: 307713
* [ARM] ldr pc,=expression should be allowed in Thumb2Peter Smith2017-07-111-8/+8
| | | | | | | | | | | This change allows the pc to be used as a destination register for the pseudo instruction LDR pc,=expression . The pseudo instruction must not be transformed into a MOV, but it can use the Thumb2 LDR (literal) instruction to a constant pool entry. See (A7.7.43 from ARMv7M ARM ARM). Differential Revision: https://reviews.llvm.org/D34751 llvm-svn: 307640
* [AsmParser] Mnemonic Spell CorrectorSjoerd Meijer2017-07-051-0/+68
| | | | | | | | | | | | | | | | | | This implements suggesting other mnemonics when an invalid one is specified, for example: $ echo "adXd r1,r2,#3" | llvm-mc -triple arm <stdin>:1:1: error: invalid instruction, did you mean: add, qadd? adXd r1,r2,#3 ^ The implementation is target agnostic, but as a first step I have added it only to the ARM backend; so the ARM backend is a good example if someone wants to enable this too for another target. Differential Revision: https://reviews.llvm.org/D33128 llvm-svn: 307148
* ARM: move some logic from processFixupValue to applyFixup.Rafael Espindola2017-06-231-9/+27
| | | | | | | | | | | | processFixupValue is called on every relaxation iteration. applyFixup is only called once at the very end. applyFixup is then the correct place to do last minute changes and value checks. While here, do proper range checks again for fixup_arm_thumb_bl. We used to do it, but dropped because of thumb2. We now do it again, but use the thumb2 range. llvm-svn: 306177
* [ARM] Create relocations for beq.w branches to ARM function syms.Florian Hahn2017-06-221-0/+39
| | | | | | | | | | | | | | | | | | Summary: The ARM ELF ABI requires the linker to do interworking for wide conditional branches from Thumb code to ARM code. That was pointed out by @peter.smith in the comments for D33436. Reviewers: rafael, peter.smith, echristo Reviewed By: peter.smith Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits, peter.smith Differential Revision: https://reviews.llvm.org/D34447 llvm-svn: 306009
* [ARM] Add .w aliases of MOV with shifted operandJohn Brawn2017-06-221-0/+16
| | | | | | | | These appear to have been simply missing. Differential Revision: https://reviews.llvm.org/D34461 llvm-svn: 305993
* Also test thumb.Rafael Espindola2017-06-221-1/+11
| | | | llvm-svn: 305976
* Simplify test.Rafael Espindola2017-06-211-40/+8
| | | | llvm-svn: 305881
* [ARM] Create relocations for unconditional branches.Florian Hahn2017-06-071-0/+25
| | | | | | | | | | | | | | | | | | | Summary: Relocations are required for unconditional branches to function symbols with different execution mode. Without this patch, incorrect branches are generated for tail calls between functions with different execution mode. Reviewers: peter.smith, rafael, echristo, kristof.beyls Reviewed By: peter.smith Subscribers: aemerson, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33898 llvm-svn: 304882
* [ARM] Support fixup for Thumb2 modified immediatePeter Smith2017-06-055-2/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds a new fixup fixup_t2_so_imm for the t2_so_imm_asmoperand "T2SOImm". The fixup permits code such as: .L1: sub r3, r3, #.L2 - .L1 .L2: to assemble in Thumb2 as well as in ARM state. The operand predicate isT2SOImm() explicitly doesn't match expressions containing :upper16: and :lower16: as expressions with these operators must match the movt and movw instructions. The test mov r0, foo2 in thumb2-diagnostics is moved to a new file as the fixup delays the error message till after the assembler has quit due to the other errors. As the mov instruction shares the t2_so_imm_asmoperand mov instructions with a non constant expression now match t2MOVi rather than t2MOVi16 so the error message is slightly different. Fixes PR28647 Differential Revision: https://reviews.llvm.org/D33492 llvm-svn: 304702
* [ARM] Create relocations for Thumb functions calling ARM fns in ELF.Florian Hahn2017-06-012-0/+78
| | | | | | | | | | | | | | | | Summary: Without using a fixup in this case, BL will be used instead of BLX to call internal ARM functions from Thumb functions. Reviewers: rafael, t.p.northover, peter.smith, kristof.beyls Reviewed By: peter.smith Subscribers: srhines, echristo, aemerson, rengolin, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33436 llvm-svn: 304413
* Re-apply r302416: [ARM] Clear the constant pool cache on explicit .ltorg ↵James Molloy2017-05-221-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | directives Re-applying now that PR32825 which was raised on the commit this fixed up is now known to have also been fixed by this commit. Original commit message: Multiple ldr pseudoinstructions with the same constant value will reuse the same constant pool entry. However, if the constant pool is explicitly flushed with a .ltorg directive, we should not try to reference constants in the previous pool any longer, since they may be out of range. This fixes assembling hand-written assembler source which repeatedly loads the same constant value, across a binary size larger than the pc-relative fixup range for ldr instructions (4096 bytes). Such assembler source already uses explicit .ltorg instructions to emit constant pools with regular intervals. However if we try to reuse constants emitted in earlier pools, they end up out of range. This makes the output of the testcase match what binutils gas does (prior to this patch, it would fail to assemble). Differential Revision: https://reviews.llvm.org/D32847 llvm-svn: 303540
* Re-apply r286006: Fix 24560: assembler does not share constant pool for ↵James Molloy2017-05-223-66/+57
| | | | | | | | | | | | | | | | | same constants Re-applying now that the open bug on this commit, PR32825, is known to be fixed. Original commit message: Summary: This patch returns the same label if the CP entry with the same value has been created. Reviewers: eli.friedman, rengolin, jmolloy Subscribers: majnemer, jmolloy, llvm-commits Differential Revision: https://reviews.llvm.org/D25804 llvm-svn: 303539
* Revert "[ARM] Clear the constant pool cache on explicit .ltorg directives"James Molloy2017-05-221-27/+0
| | | | | | | | This reverts commit r302416. This was a fixup for r286006, which has now been reverted so this doesn't apply (either in concept or in code). This commit itself has no problems, but the underlying issue it was fixing has now disappeared from the codebase. llvm-svn: 303536
* Revert "Fix 24560: assembler does not share constant pool for same constants"James Molloy2017-05-223-57/+66
| | | | | | This reverts commit r286006. It caused PR32825 and wasn't fixed. llvm-svn: 303535
* [ARM] Clear the constant pool cache on explicit .ltorg directivesMartin Storsjo2017-05-081-0/+27
| | | | | | | | | | | | | | | | | | | | | | Multiple ldr pseudoinstructions with the same constant value will reuse the same constant pool entry. However, if the constant pool is explicitly flushed with a .ltorg directive, we should not try to reference constants in the previous pool any longer, since they may be out of range. This fixes assembling hand-written assembler source which repeatedly loads the same constant value, across a binary size larger than the pc-relative fixup range for ldr instructions (4096 bytes). Such assembler source already uses explicit .ltorg instructions to emit constant pools with regular intervals. However if we try to reuse constants emitted in earlier pools, they end up out of range. This makes the output of the testcase match what binutils gas does (prior to this patch, it would fail to assemble). Differential Revision: https://reviews.llvm.org/D32847 llvm-svn: 302416
* [ARM] Add support for ORR and ORN instruction substitutionsJohn Brawn2017-05-053-0/+26
| | | | | | | | | | | | | Recently support was added for substituting one intruction for another by negating or inverting the immediate, but ORR and ORN were missed so this patch adds them. This one is slightly different to the others in that ORN only exists in thumb, so we only do the substitution in thumb. Differential Revision: https://reviews.llvm.org/D32534 llvm-svn: 302224
* [ARM] Fix handling of mapping symbols when changing sectionsJohn Brawn2017-04-201-1/+18
| | | | | | | | | | | ChangeSection incorrectly registers LastEMSInfo as belonging to the previous section, not the current section. This happens to work when changing sections using .section, as the previous section is set to the current section before the call to ChangeSection, but not when using .popsection. Differential Revision: https://reviews.llvm.org/D32225 llvm-svn: 300831
* [ARM] Add hardware build attributes in assemblerOliver Stannard2017-04-181-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the assembler, we should emit build attributes based on the target selected with command-line options. This matches the GNU assembler's behaviour. We only do this for build attributes which describe the hardware that is expected to be available, not the ones that describe ABI compatibility. This is done by moving some of the attribute emission code to ARMTargetStreamer, so that it can be shared between the assembly and code-generation code paths. Since the assembler only creates a MCSubtargetInfo, not an ARMSubtarget, the code had to be changed to check raw features, and not use the convenience functions in ARMSubtarget. If different attributes are later specified using the .eabi_attribute directive, then they will take precedence, as happens when the same .eabi_attribute is specified twice. This must be enabled by an option, because we don't want to do this when parsing inline assembly. The attributes would match the ones emitted at the start of the file, so wouldn't actually change the emitted object file, but the extra directives would be added to every inline assembly block when emitting assembly, which we'd like to avoid. The majority of the changes in the build-attributes.ll test are just re-ordering the directives, because the hardware attributes are now emitted before the ABI ones. However, I did fix one bug which I spotted: Tag_CPU_arch_profile was not being emitted for v6M. Differential revision: https://reviews.llvm.org/D31812 llvm-svn: 300547
* Add MCContext argument to MCAsmBackend::applyFixup for error reportingAlex Bradbury2017-04-051-1/+1
| | | | | | | | | | | | | | | | A number of backends (AArch64, MIPS, ARM) have been using MCContext::reportError to report issues such as out-of-range fixup values in their TgtAsmBackend. This is great, but because MCContext couldn't easily be threaded through to the adjustFixupValue helper function from its usual callsite (applyFixup), these backends ended up adding an MCContext* argument and adding another call to applyFixup to processFixupValue. Adding an MCContext parameter to applyFixup makes this unnecessary, and even better - applyFixup can take a reference to MCContext rather than a potentially null pointer. Differential Revision: https://reviews.llvm.org/D30264 llvm-svn: 299529
* Reland r298901 with modifications (reverted in r298932)Weiming Zhao2017-04-0312-18/+82
| | | | | | | | | | | | | | | | | | | Dont emit Mapping symbols for sections that contain only data. Summary: Dont emit mapping symbols for sections that contain only data. Reviewers: rengolin, weimingz, kparzysz, t.p.northover, peter.smith Reviewed By: t.p.northover Patched by Shankar Easwaran <shankare@codeaurora.org> Subscribers: alekseyshl, t.p.northover, llvm-commits Differential Revision: https://reviews.llvm.org/D30724 llvm-svn: 299392
* ARMAsmParser: clean up of isImmediate functionsSjoerd Meijer2017-04-039-44/+54
| | | | | | | | | | | | | | | | | - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
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