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* [AsmParser] Mnemonic Spell CorrectorSjoerd Meijer2017-07-051-0/+68
| | | | | | | | | | | | | | | | | | This implements suggesting other mnemonics when an invalid one is specified, for example: $ echo "adXd r1,r2,#3" | llvm-mc -triple arm <stdin>:1:1: error: invalid instruction, did you mean: add, qadd? adXd r1,r2,#3 ^ The implementation is target agnostic, but as a first step I have added it only to the ARM backend; so the ARM backend is a good example if someone wants to enable this too for another target. Differential Revision: https://reviews.llvm.org/D33128 llvm-svn: 307148
* ARM: move some logic from processFixupValue to applyFixup.Rafael Espindola2017-06-231-9/+27
| | | | | | | | | | | | processFixupValue is called on every relaxation iteration. applyFixup is only called once at the very end. applyFixup is then the correct place to do last minute changes and value checks. While here, do proper range checks again for fixup_arm_thumb_bl. We used to do it, but dropped because of thumb2. We now do it again, but use the thumb2 range. llvm-svn: 306177
* [ARM] Create relocations for beq.w branches to ARM function syms.Florian Hahn2017-06-221-0/+39
| | | | | | | | | | | | | | | | | | Summary: The ARM ELF ABI requires the linker to do interworking for wide conditional branches from Thumb code to ARM code. That was pointed out by @peter.smith in the comments for D33436. Reviewers: rafael, peter.smith, echristo Reviewed By: peter.smith Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits, peter.smith Differential Revision: https://reviews.llvm.org/D34447 llvm-svn: 306009
* [ARM] Add .w aliases of MOV with shifted operandJohn Brawn2017-06-221-0/+16
| | | | | | | | These appear to have been simply missing. Differential Revision: https://reviews.llvm.org/D34461 llvm-svn: 305993
* Also test thumb.Rafael Espindola2017-06-221-1/+11
| | | | llvm-svn: 305976
* Simplify test.Rafael Espindola2017-06-211-40/+8
| | | | llvm-svn: 305881
* [ARM] Create relocations for unconditional branches.Florian Hahn2017-06-071-0/+25
| | | | | | | | | | | | | | | | | | | Summary: Relocations are required for unconditional branches to function symbols with different execution mode. Without this patch, incorrect branches are generated for tail calls between functions with different execution mode. Reviewers: peter.smith, rafael, echristo, kristof.beyls Reviewed By: peter.smith Subscribers: aemerson, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33898 llvm-svn: 304882
* [ARM] Support fixup for Thumb2 modified immediatePeter Smith2017-06-055-2/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds a new fixup fixup_t2_so_imm for the t2_so_imm_asmoperand "T2SOImm". The fixup permits code such as: .L1: sub r3, r3, #.L2 - .L1 .L2: to assemble in Thumb2 as well as in ARM state. The operand predicate isT2SOImm() explicitly doesn't match expressions containing :upper16: and :lower16: as expressions with these operators must match the movt and movw instructions. The test mov r0, foo2 in thumb2-diagnostics is moved to a new file as the fixup delays the error message till after the assembler has quit due to the other errors. As the mov instruction shares the t2_so_imm_asmoperand mov instructions with a non constant expression now match t2MOVi rather than t2MOVi16 so the error message is slightly different. Fixes PR28647 Differential Revision: https://reviews.llvm.org/D33492 llvm-svn: 304702
* [ARM] Create relocations for Thumb functions calling ARM fns in ELF.Florian Hahn2017-06-012-0/+78
| | | | | | | | | | | | | | | | Summary: Without using a fixup in this case, BL will be used instead of BLX to call internal ARM functions from Thumb functions. Reviewers: rafael, t.p.northover, peter.smith, kristof.beyls Reviewed By: peter.smith Subscribers: srhines, echristo, aemerson, rengolin, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33436 llvm-svn: 304413
* Re-apply r302416: [ARM] Clear the constant pool cache on explicit .ltorg ↵James Molloy2017-05-221-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | directives Re-applying now that PR32825 which was raised on the commit this fixed up is now known to have also been fixed by this commit. Original commit message: Multiple ldr pseudoinstructions with the same constant value will reuse the same constant pool entry. However, if the constant pool is explicitly flushed with a .ltorg directive, we should not try to reference constants in the previous pool any longer, since they may be out of range. This fixes assembling hand-written assembler source which repeatedly loads the same constant value, across a binary size larger than the pc-relative fixup range for ldr instructions (4096 bytes). Such assembler source already uses explicit .ltorg instructions to emit constant pools with regular intervals. However if we try to reuse constants emitted in earlier pools, they end up out of range. This makes the output of the testcase match what binutils gas does (prior to this patch, it would fail to assemble). Differential Revision: https://reviews.llvm.org/D32847 llvm-svn: 303540
* Re-apply r286006: Fix 24560: assembler does not share constant pool for ↵James Molloy2017-05-223-66/+57
| | | | | | | | | | | | | | | | | same constants Re-applying now that the open bug on this commit, PR32825, is known to be fixed. Original commit message: Summary: This patch returns the same label if the CP entry with the same value has been created. Reviewers: eli.friedman, rengolin, jmolloy Subscribers: majnemer, jmolloy, llvm-commits Differential Revision: https://reviews.llvm.org/D25804 llvm-svn: 303539
* Revert "[ARM] Clear the constant pool cache on explicit .ltorg directives"James Molloy2017-05-221-27/+0
| | | | | | | | This reverts commit r302416. This was a fixup for r286006, which has now been reverted so this doesn't apply (either in concept or in code). This commit itself has no problems, but the underlying issue it was fixing has now disappeared from the codebase. llvm-svn: 303536
* Revert "Fix 24560: assembler does not share constant pool for same constants"James Molloy2017-05-223-57/+66
| | | | | | This reverts commit r286006. It caused PR32825 and wasn't fixed. llvm-svn: 303535
* [ARM] Clear the constant pool cache on explicit .ltorg directivesMartin Storsjo2017-05-081-0/+27
| | | | | | | | | | | | | | | | | | | | | | Multiple ldr pseudoinstructions with the same constant value will reuse the same constant pool entry. However, if the constant pool is explicitly flushed with a .ltorg directive, we should not try to reference constants in the previous pool any longer, since they may be out of range. This fixes assembling hand-written assembler source which repeatedly loads the same constant value, across a binary size larger than the pc-relative fixup range for ldr instructions (4096 bytes). Such assembler source already uses explicit .ltorg instructions to emit constant pools with regular intervals. However if we try to reuse constants emitted in earlier pools, they end up out of range. This makes the output of the testcase match what binutils gas does (prior to this patch, it would fail to assemble). Differential Revision: https://reviews.llvm.org/D32847 llvm-svn: 302416
* [ARM] Add support for ORR and ORN instruction substitutionsJohn Brawn2017-05-053-0/+26
| | | | | | | | | | | | | Recently support was added for substituting one intruction for another by negating or inverting the immediate, but ORR and ORN were missed so this patch adds them. This one is slightly different to the others in that ORN only exists in thumb, so we only do the substitution in thumb. Differential Revision: https://reviews.llvm.org/D32534 llvm-svn: 302224
* [ARM] Fix handling of mapping symbols when changing sectionsJohn Brawn2017-04-201-1/+18
| | | | | | | | | | | ChangeSection incorrectly registers LastEMSInfo as belonging to the previous section, not the current section. This happens to work when changing sections using .section, as the previous section is set to the current section before the call to ChangeSection, but not when using .popsection. Differential Revision: https://reviews.llvm.org/D32225 llvm-svn: 300831
* [ARM] Add hardware build attributes in assemblerOliver Stannard2017-04-181-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the assembler, we should emit build attributes based on the target selected with command-line options. This matches the GNU assembler's behaviour. We only do this for build attributes which describe the hardware that is expected to be available, not the ones that describe ABI compatibility. This is done by moving some of the attribute emission code to ARMTargetStreamer, so that it can be shared between the assembly and code-generation code paths. Since the assembler only creates a MCSubtargetInfo, not an ARMSubtarget, the code had to be changed to check raw features, and not use the convenience functions in ARMSubtarget. If different attributes are later specified using the .eabi_attribute directive, then they will take precedence, as happens when the same .eabi_attribute is specified twice. This must be enabled by an option, because we don't want to do this when parsing inline assembly. The attributes would match the ones emitted at the start of the file, so wouldn't actually change the emitted object file, but the extra directives would be added to every inline assembly block when emitting assembly, which we'd like to avoid. The majority of the changes in the build-attributes.ll test are just re-ordering the directives, because the hardware attributes are now emitted before the ABI ones. However, I did fix one bug which I spotted: Tag_CPU_arch_profile was not being emitted for v6M. Differential revision: https://reviews.llvm.org/D31812 llvm-svn: 300547
* Add MCContext argument to MCAsmBackend::applyFixup for error reportingAlex Bradbury2017-04-051-1/+1
| | | | | | | | | | | | | | | | A number of backends (AArch64, MIPS, ARM) have been using MCContext::reportError to report issues such as out-of-range fixup values in their TgtAsmBackend. This is great, but because MCContext couldn't easily be threaded through to the adjustFixupValue helper function from its usual callsite (applyFixup), these backends ended up adding an MCContext* argument and adding another call to applyFixup to processFixupValue. Adding an MCContext parameter to applyFixup makes this unnecessary, and even better - applyFixup can take a reference to MCContext rather than a potentially null pointer. Differential Revision: https://reviews.llvm.org/D30264 llvm-svn: 299529
* Reland r298901 with modifications (reverted in r298932)Weiming Zhao2017-04-0312-18/+82
| | | | | | | | | | | | | | | | | | | Dont emit Mapping symbols for sections that contain only data. Summary: Dont emit mapping symbols for sections that contain only data. Reviewers: rengolin, weimingz, kparzysz, t.p.northover, peter.smith Reviewed By: t.p.northover Patched by Shankar Easwaran <shankare@codeaurora.org> Subscribers: alekseyshl, t.p.northover, llvm-commits Differential Revision: https://reviews.llvm.org/D30724 llvm-svn: 299392
* ARMAsmParser: clean up of isImmediate functionsSjoerd Meijer2017-04-039-44/+54
| | | | | | | | | | | | | | | | | - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
* Revert "Dont emit Mapping symbols for sections that contain only data."Weiming Zhao2017-03-2812-82/+18
| | | | | | | | It breaks some lld tests. This reverts commit 3a50eea6d9732ab40e9a7aebe6be777b53a8b35c. llvm-svn: 298932
* Dont emit Mapping symbols for sections that contain only data.Weiming Zhao2017-03-2812-18/+82
| | | | | | | | | | | | | | | | | Summary: Dont emit mapping symbols for sections that contain only data. Patched by Shankar Easwaran <shankare@codeaurora.org> Reviewers: rengolin, peter.smith, weimingz, kparzysz, t.p.northover Reviewed By: t.p.northover Subscribers: t.p.northover, llvm-commits Differential Revision: https://reviews.llvm.org/D30724 llvm-svn: 298901
* [ARM] [Assembler] Support negative immediates for A32, T32 and T16Sanne Wouda2017-03-214-0/+175
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: To support negative immediates for certain arithmetic instructions, the instruction is converted to the inverse instruction with a negated (or inverted) immediate. For example, "ADD r0, r1, #FFFFFFFF" cannot be encoded as an ADD instruction. However, "SUB r0, r1, #1" is equivalent. These conversions are different from instruction aliases. An alias maps several assembler instructions onto one encoding. A conversion, however, maps an *invalid* instruction--e.g. with an immediate that cannot be represented in the encoding--to a different (but equivalent) instruction. Several instructions with negative immediates were being converted already, but this was not systematically tested, nor did it cover all instructions. This patch implements all possible substitutions for ARM, Thumb1 and Thumb2 assembler and adds tests. It also adds a feature flag (-mattr=+no-neg-immediates) to turn these substitutions off. This is helpful for users who want their code to assemble to exactly what they wrote. Reviewers: t.p.northover, rovka, samparker, javed.absar, peter.smith, rengolin Reviewed By: javed.absar Subscribers: aadg, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D30571 llvm-svn: 298380
* [ARM] Fix triple format in test branch disassemble testAndre Vieira2017-03-172-7/+22
| | | | | | | | | | | | Fixing triple format in the tests added for the branch label fix for Thumb Targets. Also recommitting previously approved patch, see https://reviews.llvm.org/D30943. Reviewed by: samparker Differential Revision: https://reviews.llvm.org/D30987 llvm-svn: 298056
* Reverting r297821 due to breaking lld test.Sam Parker2017-03-152-64/+49
| | | | llvm-svn: 297838
* [ARM] Fix for branch label disassembly for ThumbSam Parker2017-03-152-49/+64
| | | | | | | | | | | | | | | | | Different MCInstrAnalysis classes for arm and thumb mode, each with their own evaluateBranch implementation. I added a test case and fixed the coff-relocations test to use '<label>:' rather than '<label>' in the CHECK-LABEL entries, since the ones without the colon would match branch targets. Might be worth noticing that llvm-objdump does not lookup the relocation and thus assigns it a target depending on the encoded immediate which #0, so it thinks it branches to the next instruction. Committed on behalf of Andre Vieira (avieira). Differential Revision: https://reviews.llvm.org/D30943 llvm-svn: 297821
* [ARM] Diagnose ARM MOVT without :lower16: or :upper16: expressionOliver Stannard2017-03-141-0/+3
| | | | | | | | | | | This instruction was missing from the list of opcodes that we check, so we were hitting an llvm_unreachable in ARMMCCodeEmitter.cpp for the ARM MOVT instruction, rather than the diagnostic that is emitted for the other MOVW/MOVT instructions. Differential revision: https://reviews.llvm.org/D30936 llvm-svn: 297739
* [Assembler] Add location info to unary expressions.Sanne Wouda2017-03-101-1/+1
| | | | | | | | | | | | | | | | | Summary: This is a continuation of D28861. Add an SMLoc to MCUnaryExpr such that a better diagnostic can be given in case of an error in later stages of assembling. Reviewers: rengolin, grosbach, javed.absar, olista01 Reviewed By: olista01 Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30581 llvm-svn: 297454
* [ARM] Remove t2xtpk feature from testsSam Parker2017-03-091-2/+2
| | | | | | | | | I previously removed the T2XtPk feature from the ARM backend, but it looks like I missed some of the tests that were using the feature. Differential Revision: https://reviews.llvm.org/D30778 llvm-svn: 297386
* [ARM] remove FIXMEs and add vcmp MC testSjoerd Meijer2017-03-091-0/+12
| | | | | | | | | Minor cleanup in ARMInstrVFP.td: removed some FIXMEs and added a MC test for vcmp that was actually missing. Differential Revision: https://reviews.llvm.org/D30745 llvm-svn: 297376
* [ARM] Split up lsl-zero test into two testsJohn Brawn2017-03-082-99/+105
| | | | | | | | On Windows stderr and stdout happen to get interleaved in a way that causes the test to fail, so split it up into a test that checks for errors and a test that doesn't. llvm-svn: 297273
* [ARM] Correct handling of LSL #0 in an IT blockJohn Brawn2017-03-071-0/+14
| | | | | | | | | | | The check for LSL #0 in an IT block was checking if operand 4 was zero, but operand 4 is the condition code operand so it was actually checking for LSLEQ. Fix this by checking operand 3, which really is the immediate operand, and add some tests. Differential Revision: https://reviews.llvm.org/D30692 llvm-svn: 297142
* [ARM] Fix bash-ism in testOliver Stannard2017-03-011-2/+2
| | | | llvm-svn: 296610
* [ARM] Fix parsing of special register masksOliver Stannard2017-03-011-0/+11
| | | | | | | | | | | | This parsing code was incorrectly checking for invalid characters, so an invalid instruction like: msr spsr_w, r0 would be emitted as: msr spsr_cxsf, r0 Differential revision: https://reviews.llvm.org/D30462 llvm-svn: 296607
* [DWARFv5] llvm-mc support for new unit header.Paul Robinson2017-02-281-15/+22
| | | | | | | | | This is for running the assembler with -g (to emit DWARF describing the assembler source). Differential Revision: http://reviews.llvm.org/D30475 llvm-svn: 296541
* [Assembler] Add test for !srcloc references in assembler diagsSanne Wouda2017-02-281-0/+37
| | | | | | | | | | | | | | | | | | | | | | | Summary: clang adds !srcloc metadata to inline assembly in LLVM bitcode generated for inline assembly in C. The value of this !srcloc is passed to the diagnostics handler if the inline assembly generates a diagnostic. clang is able to turn this cookie back to a location in the C source file. To test this functionality without a dependency, make llc print the !srcloc metadata if it is present. The added test uses this mechanism to test that the correct !srclocs are passed to the diag handler. Reviewers: rengolin, rnk, echristo, grosbach, mehdi_amini Reviewed By: mehdi_amini Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D30167 llvm-svn: 296465
* [ARM] Diagnose PC-writing instructions in IT blocksOliver Stannard2017-02-283-4/+63
| | | | | | | | | | | | In Thumb2, instructions which write to the PC are UNPREDICTABLE if they are in an IT block but not the last instruction in the block. Previously, we only diagnosed this for LDM instructions, this patch extends the diagnostic to cover all of the relevant instructions. Differential Revision: https://reviews.llvm.org/D30398 llvm-svn: 296459
* [ARM] LSL #0 is an alias of MOVJohn Brawn2017-02-272-0/+167
| | | | | | | | | | | | | | | | | | | | | | | | Currently we handle this correctly in arm, but in thumb we don't which leads to an unpredictable instruction being emitted for LSL #0 in an IT block and SP not being permitted in some cases when it should be. For the thumb2 LSL we can handle this by making LSL #0 an alias of MOV in the .td file, but for thumb1 we need to handle it in checkTargetMatchPredicate to get the IT handling right. We also need to adjust the handling of MOV rd, rn, LSL #0 to avoid generating the 16-bit encoding in an IT block. We should also adjust it to allow SP in the same way that it is allowed in MOV rd, rn, but I haven't done that here because it looks like it would take quite a lot of work to get right. Additionally correct the selection of the 16-bit shift instructions in processInstruction, where it was checking if the two registers were equal when it should have been checking if they were low. It appears that previously this code was never executed and the 16-bit encoding was selected by default, but the other changes I've done here have somehow made it start being used. Differential Revision: https://reviews.llvm.org/D30294 llvm-svn: 296342
* [ARM] Correct SP/PC handling in t2MOVrJohn Brawn2017-02-211-0/+100
| | | | | | Add a missing test that I forgot to svn add in my previous commit llvm-svn: 295734
* Fix inline-asm-diags.ll on Windows, give it a triple to avoid WoA thumb ↵Reid Kleckner2017-02-081-1/+1
| | | | | | confusion llvm-svn: 294496
* Move inline asm diags tests to an ARM directory.Sanne Wouda2017-02-081-0/+9
| | | | | | | The assembler syntaxes (and parsers) differ too much to expect this test to pass for all of them. llvm-svn: 294475
* [ARM] Avoid using ARM instructions in Thumb modeSam Parker2017-01-311-0/+6
| | | | | | | | | | | | | | The Requires class overrides the target requirements of an instruction, rather than adding to them, so all ARM instructions need to include the IsARM predicate when they have overwitten requirements. This caused the swp and swpb instructions to be allowed in thumb mode assembly, and the ARM encoding of CDP to be selected in codegen (which is different for conditional instructions). Differential Revision: https://reviews.llvm.org/D29283 llvm-svn: 293634
* Fix some broken CHECK lines.Benjamin Kramer2017-01-222-2/+2
| | | | | | The colon is important. llvm-svn: 292761
* [Assembler] Improve error when unable to evaluate expression.Chad Rosier2017-01-191-6/+6
| | | | | | | | | Add a SMLoc to MCExpr. Most code does not generate or consume the SMLoc (yet). Patch by Sanne Wouda <sanne.wouda@arm.com>! Differential Revision: https://reviews.llvm.org/D28861 llvm-svn: 292515
* Fix aliases to thumbfunc-based exprs to be thumbfunc.Evgeniy Stepanov2017-01-191-0/+10
| | | | | | | | | If F is a Thumb function symbol, and G = F + const, and G is a function symbol, then G is Thumb. Because what else could it be? Differential Revision: https://reviews.llvm.org/D28878 llvm-svn: 292514
* [Assembler] Fix crash when assembling .quad for AArch32.Chad Rosier2017-01-181-0/+9
| | | | | | | | | | | A 64-bit relocation does not exist in 32-bit ARMELF. Report an error instead of crashing. PR23870 Patch by Sanne Wouda (sanwou01). Differential Revision: https://reviews.llvm.org/D28851 llvm-svn: 292373
* Drive by typo fixMatthias Braun2017-01-092-2/+2
| | | | llvm-svn: 291482
* [MC/COFF] Fix a test to actually check the relocation.Davide Italiano2017-01-041-1/+1
| | | | | | Inspired by r290953 + grep -R 'CHCEK'. llvm-svn: 290958
* [Assembler] Better error messages for .org directiveOliver Stannard2016-12-142-10/+14
| | | | | | | | | | | | | | | | | | | | | Currently, the error messages we emit for the .org directive when the expression is not absolute or is out of range do not include the line number of the directive, so it can be hard to track down the problem if a file contains many .org directives. This patch stores the source location in the MCOrgFragment, so that it can be used for diagnostics emitted during layout. Since layout is an iterative process, and the errors are detected during each iteration, it would have been possible for errors to be reported multiple times. To prevent this, I've made the assembler bail out after each iteration if any errors have been reported. This will still allow multiple unrelated errors to be reported in the common case where they are all detected in the first round of layout. Differential Revision: https://reviews.llvm.org/D27411 llvm-svn: 289643
* [ARM] Better error message for invalid flag-preserving Thumb1 instsOliver Stannard2016-12-061-1/+1
| | | | | | | | | | When we see a non flag-setting instruction for which only the flag-setting version is available in Thumb1, we should give a better error message than "invalid instruction". Differential Revision: https://reviews.llvm.org/D27414 llvm-svn: 288805
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