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* MC: ensure that we have a section before accessing itSaleem Abdulrasool2016-11-221-0/+13
| | | | | | | | | | | | We would attempt to access the symbol section without ensuring that the symbol was not absolute. When the assembler referenced relocation is not evaluated to the absolute, but when we record the relocation, we would query the section. Because the symbol is absolute, it does not have a section associated with it, triggering an assertion. Just be more careful about the access of the section. Addresses PR31064! llvm-svn: 287619
* [ARM] Thumb2 LDR (literal) should accept PC as the destinationOliver Stannard2016-11-101-0/+5
| | | | | | | | | The version of this instruction with the .w suffix already correctly accepts this, but the alias without the .w did not. Differential Revision: https://reviews.llvm.org/D26499 llvm-svn: 286446
* Fix 24560: assembler does not share constant pool for same constantsWeiming Zhao2016-11-043-66/+57
| | | | | | | | | | | | Summary: This patch returns the same label if the CP entry with the same value has been created. Reviewers: eli.friedman, rengolin, jmolloy Subscribers: majnemer, jmolloy, llvm-commits Differential Revision: https://reviews.llvm.org/D25804 llvm-svn: 286006
* Emit S_COMPILE3 record once per TU rather than once per functionAdrian McCarthy2016-11-021-4/+4
| | | | | | This has some ripple effects in several tests. llvm-svn: 285862
* [ARM][MC] Cleanup ARM Target Assembly ParserNirav Dave2016-11-022-1/+171
| | | | | | | | | | | | | | Summary: Correctly parse end-of-statement tokens and handle preprocessor end-of-line comments in ARM assembly processor. Reviewers: rnk, majnemer Subscribers: aemerson, rengolin, llvm-commits Differential Revision: https://reviews.llvm.org/D26152 llvm-svn: 285830
* Emit S_COMPILE3 CodeView recordAdrian McCarthy2016-09-201-4/+4
| | | | | | | | | | CodeView has an S_COMPILE3 record to identify the compiler and source language of the compiland. This record comes first in the debug$S section for the compiland. The debuggers rely on this record to know the source language of the code. There was a little test fallout from introducing a new record into the symbols subsection. Differential Revision: https://reviews.llvm.org/D24317 llvm-svn: 281990
* [Thumb] Set correct initial mapping symbol for big-endian thumbOliver Stannard2016-09-191-0/+9
| | | | | | | | | | The initial mapping symbol state is set from the triple, but we only checked for the little-endian thumb triple, so could end up with an ARM mapping symbol for big-endian thumb. Differential Revision: https://reviews.llvm.org/D24553 llvm-svn: 281894
* [ARM] Support ldr.w in pseudo instruction ldr rd,=immediatePeter Smith2016-09-131-0/+71
| | | | | | | | | | | | The changes made in r269352, r269353 and r269354 to support the transformation of the ldr rd,=immediate to mov introduced a regression from 3.8 (ldr.w rd, =immediate) not supported. This change puts support back in for ldr.w by means of a t2InstAlias for the .w form. The .w is ignored in ARM state and propagated to the ldr in Thumb2. llvm-svn: 281319
* [Thumb1] Add relocations for fixups fixup_arm_thumb_{br,bcc}James Molloy2016-09-051-0/+21
| | | | | | | | These need to be mapped through to R_ARM_THM_JUMP{11,8} respectively. Fixes PR30279. llvm-svn: 280651
* [SimplifyCFG] Handle tail-sinking of more than 2 incoming branchesJames Molloy2016-09-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was a real restriction in the original version of SinkIfThenCodeToEnd. Now it's been rewritten, the restriction can be lifted. As part of this, we handle a very common and useful case where one of the incoming branches is actually conditional. Consider: if (a) x(1); else if (b) x(2); This produces the following CFG: [if] / \ [x(1)] [if] | | \ | | \ | [x(2)] | \ | / [ end ] [end] has two unconditional predecessor arcs and one conditional. The conditional refers to the implicit empty 'else' arc. This same pattern can also be caused by an empty default block in a switch. We can't sink the call to x() down to end because no call to x() happens on the third incoming arc (assume that x() has sideeffects for the sake of argument; if something is safe to speculate we could indeed sink nevertheless but this cannot happen in the general case and causes many extra selects). We are now able to detect this case and split off the unconditional arcs to a common successor: [if] / \ [x(1)] [if] | | \ | | \ | [x(2)] | \ / | [sink.split] | \ / [ end ] Now we can sink the call to x() into %sink.split. This can cause significant code simplification in many testcases. llvm-svn: 280364
* Revert "[SimplifyCFG] Handle tail-sinking of more than 2 incoming branches"James Molloy2016-08-311-2/+2
| | | | | | This reverts commit r280217. r280216 caused buildbot failures - backing out the entire chain. llvm-svn: 280233
* [SimplifyCFG] Handle tail-sinking of more than 2 incoming branchesJames Molloy2016-08-311-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was a real restriction in the original version of SinkIfThenCodeToEnd. Now it's been rewritten, the restriction can be lifted. As part of this, we handle a very common and useful case where one of the incoming branches is actually conditional. Consider: if (a) x(1); else if (b) x(2); This produces the following CFG: [if] / \ [x(1)] [if] | | \ | | \ | [x(2)] | \ | / [ end ] [end] has two unconditional predecessor arcs and one conditional. The conditional refers to the implicit empty 'else' arc. This same pattern can also be caused by an empty default block in a switch. We can't sink the call to x() down to end because no call to x() happens on the third incoming arc (assume that x() has sideeffects for the sake of argument; if something is safe to speculate we could indeed sink nevertheless but this cannot happen in the general case and causes many extra selects). We are now able to detect this case and split off the unconditional arcs to a common successor: [if] / \ [x(1)] [if] | | \ | | \ | [x(2)] | \ / | [sink.split] | \ / [ end ] Now we can sink the call to x() into %sink.split. This can cause significant code simplification in many testcases. llvm-svn: 280217
* ARM: by default don't set the Thumb bit on MachO relocated values.Tim Northover2016-08-252-0/+31
| | | | | | | | | | | | | Its existence is largely historical, apparently we tried to make ARM object files look maybe-almost-possibly runnable by putting our best guess at the actual value into relocated locations. Of course, the real linker then comes along and can completely change things. But it should only be there for word-sized and movw/movt relocations. It can't be encoded in branch relocations, and I've seen it mess up validity calculations twice in the last couple of weeks so the default is clearly problematic. llvm-svn: 279773
* ARM: don't diagnose cbz/cbnz to Thumb functions.Tim Northover2016-08-242-0/+15
| | | | | | | | A branch-distance to a Thumb function shouldn't be forced to be odd for CBZ/CBNZ instructions because (assuming it's within range), it's going to be a valid, even offset. llvm-svn: 279665
* Correct the upper bound for a CBZ/CBNZ branch target.Prakhar Bahuguna2016-08-161-1/+13
| | | | | | | | | | | | | Summary: Fix for the upper bound check that was causing a build failure. Reviewers: olista01, rengolin, t.p.northover Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23501 llvm-svn: 278789
* [Thumb] Validate branch target for CBZ/CBNZ instructions.Prakhar Bahuguna2016-08-162-0/+36
| | | | | | | | | | | | | | | | | Summary: The assembler currently does not check the branch target for CBZ/CBNZ instructions, which only permit branching forwards with a positive offset. This adds validation for the branch target to ensure negative PC-relative offsets are not encoded into the instruction, whether specified as a literal or as an assembler symbol. Reviewers: rengolin, t.p.northover Subscribers: llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D23312 llvm-svn: 278788
* Revert "[Thumb] Validate branch target for CBZ/CBNZ instructions."Matthias Braun2016-08-152-36/+0
| | | | | | | | | | | This currently breaks the greendragon clang-stage1-configure-RA/ and brotli. It is probably just uncovering a pre-existing problem. Reverting temporarily to get the buildbots green again. A reduced testcase will follow shortly. This reverts commit r278659. llvm-svn: 278711
* [Thumb] Validate branch target for CBZ/CBNZ instructions.Prakhar Bahuguna2016-08-152-0/+36
| | | | | | | | | | | | | | | | | Summary: The assembler currently does not check the branch target for CBZ/CBNZ instructions, which only permit branching forwards with a positive offset. This adds validation for the branch target to ensure negative PC-relative offsets are not encoded into the instruction, whether specified as a literal or as an assembler symbol. Reviewers: rengolin, t.p.northover Subscribers: llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D23312 llvm-svn: 278659
* Fix handling of end-of-line preprocessor comments Attempt 2Nirav Dave2016-08-021-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | Attempt 2: Retryign after Tsan.mman test fix. Attempt 1: Recommitting after fixing test. When parsing assembly where the line comment syntax is not hash, the lexer cannot distinguish between hash's that start a hash line comment and one that is part of an assembly statement and must be distinguished during parsing. Previously, this was incompletely handled by not checking for EndOfStatement at the end of statements and interpreting hash prefixed statements as comments. Change EndOfStatement Parsing to check for Hash comments and reintroduce Hash statement parsing to catch previously handled cases. Reviewers: rnk, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23017 llvm-svn: 277501
* Revert "[MC] Fix handling of end-of-line preprocessor comments"Nirav Dave2016-08-021-10/+0
| | | | | | | | Causes TSan failure on PPC64 This reverts commit r277459. llvm-svn: 277468
* [MC] Fix handling of end-of-line preprocessor commentsNirav Dave2016-08-021-0/+10
| | | | | | | | | | | | | | | | | | | | | | Recommitting after fixing test. When parsing assembly where the line comment syntax is not hash, the lexer cannot distinguish between hash's that start a hash line comment and one that is part of an assembly statement and must be distinguished during parsing. Previously, this was incompletely handled by not checking for EndOfStatement at the end of statements and interpreting hash prefixed statements as comments. Change EndOfStatement Parsing to check for Hash comments and reintroduce Hash statement parsing to catch previously handled cases. Reviewers: rnk, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23017 llvm-svn: 277459
* Revert r277408 and r277407Bruno Cardoso Lopes2016-08-021-10/+0
| | | | | | | | | | Revert r277408 "Fix test from rL277407." Revert r277407 "[MC] Fix handling of end-of-line preprocessor comments" This is currently breaking: http://lab.llvm.org:8080/green/job/clang-stage1-configure-RA_check/20731 llvm-svn: 277412
* Fix test from rL277407.Nirav Dave2016-08-021-3/+3
| | | | llvm-svn: 277408
* [MC] Fix handling of end-of-line preprocessor commentsNirav Dave2016-08-021-0/+10
| | | | | | | | | | | | | | | | | | | | | Summary: When parsing assembly where the line comment syntax is not hash, the lexer cannot distinguish between hash's that start a hash line comment and one that is part of an assembly statement and must be distinguished during parsing. Previously, this was incompletely handled by not checking for EndOfStatement at the end of statements and interpreting hash prefixed statements as comments. Change EndOfStatement Parsing to check for Hash comments and reintroduce Hash statement parsing to catch previously handled cases. Reviewers: rnk, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23017 llvm-svn: 277407
* Add removed inline-assembly-comment test from r277146Nirav Dave2016-08-011-0/+22
| | | | llvm-svn: 277349
* [ARM] Check that the thumb COFF segment flag gets set on thumb windowsRenato Golin2016-07-271-0/+16
| | | | | | Patch by Martin Storsjö. llvm-svn: 276877
* [ARM] Set a non-conflicting comment character for assembly in MSVC modeRenato Golin2016-07-271-0/+13
| | | | | | | | | | | | | | | | | | | | | | | Currently, for ARMCOFFMCAsmInfoMicrosoft, no comment character is set, thus the idefault, '#', is used. The hash character doesn't work as comment character in ARM assembly, since '#' is used for immediate values. The comment character is set to ';', which is the comment character used by MS armasm.exe. (The microsoft armasm.exe uses a different directive syntax than what LLVM currently supports though, similar to ARM's armasm.) This allows inline assembly with immediate constants to be built (and brings the assembly output from clang -S closer to being possible to assemble). A test is added that verifies that ';' is correctly interpreted as comments in this mode, and verifies that assembling code that includes literal constants with a '#' works. Patch by Martin Storsjö. llvm-svn: 276859
* [ARM] Adds test for immediate encodingRenato Golin2016-07-271-0/+29
| | | | | | | | | The encoding of expressions as immediates wasn't correct, and was reported in PR23000. However, we have done some refactoring on how immediates are handled and now it seems the problem is fixed. This is a test just to make sure it won't regress again. llvm-svn: 276858
* [ARM] Improve error messages for .arch_extension directiveOliver Stannard2016-07-261-0/+25
| | | | | | | | | | | | - More informative message when extension name is not an identifier token. - Stop parsing directive if extension is unknown (avoid duplicate error messages). - Report unsupported extensions with a source location, rather than report_fatal_error. Differential Revision: https://reviews.llvm.org/D22806 llvm-svn: 276748
* [ARM] Implement -mimplicit-it assembler optionOliver Stannard2016-07-262-0/+482
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This option, compatible with gas's -mimplicit-it, controls the generation/checking of implicit IT blocks in ARM/Thumb assembly. This option allows two behaviours that were not possible before: - When in ARM mode, emit a warning when assembling a conditional instruction that is not in an IT block. This is enabled with -mimplicit-it=never and -mimplicit-it=thumb. - When in Thumb mode, automatically generate IT instructions when an instruction with a condition code appears outside of an IT block. This is enabled with -mimplicit-it=thumb and -mimplicit-it=always. The default option is -mimplicit-it=arm, which matches the existing behaviour (allow conditional ARM instructions outside IT blocks without warning, and error if a conditional Thumb instruction is outside an IT block). The general strategy for generating IT blocks in Thumb mode is to keep a small list of instructions which should be in the IT block, and only emit them when we encounter something in the input which means we cannot continue the block. This could be caused by: - A non-predicable instruction - An instruction with a condition not compatible with the IT block - The IT block already contains 4 instructions - A branch-like instruction (including ALU instructions with the PC as the destination), which cannot appear in the middle of an IT block - A label (branching into an IT block is not legal) - A change of section, architecture, ISA, etc - The end of the assembly file. Some of these, such as change of section and end of file, are parsed outside of the ARM asm parser, so I've added a new virtual function to AsmParser to ensure any previously-parsed instructions have been emitted. The ARM implementation of this flushes the currently pending IT block. We now have to try instruction matching up to 3 times, because we cannot know if the current IT block is valid before matching, and instruction matching changes depending on the IT block state (due to the 16-bit ALU instructions, which set the flags iff not in an IT block). In the common case of not having an open implicit IT block and the instruction being matched not needing one, we still only have to run the matcher once. I've removed the ITState.FirstCond variable, because it does not store any information that isn't already represented by CurPosition. I've also updated the comment on CurPosition to accurately describe it's meaning (which this patch doesn't change). Differential Revision: https://reviews.llvm.org/D22760 llvm-svn: 276747
* ARM: move feature for Thumb2 pkhbt/pkhtb onto architectures.Tim Northover2016-07-191-0/+17
| | | | | | | | | | | There's not much functional change, but it really is an architectural feature (on v6T2, v7A, v7R and v7EM) rather than something each CPU implements individually. The main functional change is the default behaviour you get when specifying only "-triple". llvm-svn: 276013
* Add support for tlsldm assembler operator to ARM targetPeter Smith2016-07-191-4/+10
| | | | | | | | | | | | | | | | | | | | The standard local dynamic model for TLS on ARM systems needs two relocations: - R_ARM_TLS_LDM32 (module idx) - R_ARM_TLS_LDO32 (offset of object from origin of module TLS block) In GNU style assembler we use symbol(tlsldm) and symbol(tlsldo) to produce these relocations. llvm-mc for ARM supports symbol(tlsldo) but does not support symbol(tlsldm). This patch wires up the existing symbol(tlsldm) to R_ARM_TLS_LDM32. TLS for ARM is defined in Addenda to, and Errata in, the ABI for the ARM Architecture Differential Revision: https://reviews.llvm.org/D22461 llvm-svn: 275977
* ARM: fix vmov.i64 immediate validity checkTim Northover2016-07-141-0/+3
| | | | | | Typo meant we were only checking the low byte (repeatedly). llvm-svn: 275437
* ARM: validate immediate branch targets in AsmParser.Tim Northover2016-07-114-0/+71
| | | | | | | | | | Immediate branch targets aren't commonly used, but if they are we should make sure they can actually be encoded. This means they must be divisible by 2 when targeting Thumb mode, and by 4 when targeting ARM mode. Also do a little naming cleanup while I was changing everything around anyway. llvm-svn: 275116
* [ARM] Accept conditional versions of BXNS and BLXNSOliver Stannard2016-06-071-0/+14
| | | | | | | | | These instructions end in "S" but are not flag-setting, so they need including in the list of special cases in the assembly parser. Differential Revision: http://reviews.llvm.org/D21077 llvm-svn: 272015
* [ARM] Incorrect relocation type for Thumb2 B<cond>.wPeter Smith2016-06-071-1/+1
| | | | | | | | | | | | | | | | | The Thumb2 conditional branch B<cond>.W has a different encoding (T3) to the unconditional branch B.W (T4) as it needs to record <cond>. As the encoding is different the B<cond>.W is given a different relocation type. ELF for the ARM Architecture 4.6.1.6 (Table-13) states that R_ARM_THM_JUMP19 should be used for B<cond>.W. At present the MC layer is using the R_ARM_THM_JUMP24 from B.W. This change makes B<cond>.W use R_ARM_THM_JUMP19 and alters the existing test that checks for R_ARM_THM_JUMP24 to expect R_ARM_THM_JUMP19. llvm-svn: 271997
* RAS extensions are part of ARMv8.2-A. This change enables them by introducing aSjoerd Meijer2016-06-031-0/+6
| | | | | | | | | | new instruction to ARM and AArch64 targets and several system registers. Patch by: Roger Ferrer Ibanez and Oliver Stannard Differential Revision: http://reviews.llvm.org/D20282 llvm-svn: 271670
* Don't pass relocation-model= to tests that don't need it.Rafael Espindola2016-05-181-1/+1
| | | | | | | Very few things in MC itself use the option. Most of the code that that uses it could be move to CodeGen. llvm-svn: 269871
* [ARM] ARM mov InstAlias for MOVW lacks HasV6T2Renato Golin2016-05-171-0/+5
| | | | | | | | | | | | | | The movw instruction is only available in ARM state for V6T2 and above. The MOVi16 instruction has requirement HasV6T2 but the InstAlias for mov rd, imm where the operand is imm0_65535_expr:$imm does not. This means that movw can incorrectly be used in ARMv4 and ARMv5 by writing mov rd, 0x1234. The simple fix is to the requirement HasV6T2 to the InstAlias. Tests added to not-armv4.s. Patch by Peter Smith. llvm-svn: 269761
* [ARM] Support and tests for transform of LDR rt, = to MOVRenato Golin2016-05-125-8/+325
| | | | | | | | | | | | | | | | | | | | | | | | | | This change implements the transformation in processInstruction() for the LDR rt, =expression to MOV rt, expression when the expression can be evaluated and can fit into the immediate field of the MOV or a MVN. Across the ARM and Thumb instruction sets there are several cases to consider, each with a different range of representatble constants. In ARM we have: * Modified immediate (All ARM architectures) * MOVW (v6t2 and above) In Thumb we have: * Modified immediate (v6t2, v7m and v8m.mainline) * MOVW (v6t2, v7m, v8.mainline and v8m.baseline) * Narrow Thumb MOV that can be used in an IT block (non flag-setting) If the immediate fits any of the available alternatives then we make the transformation. Fixes 25722. Patch by Peter Smith. llvm-svn: 269354
* [ARM] Fixup tests to take into account mov translation. NFC.Renato Golin2016-05-125-54/+54
| | | | | | | | | | | | | Alter instances in the test-suite that use immediates that can be represented in the immediate field of a MOV. The reason for doing this is that when the LDR rt,=imm transformation to MOV rt, imm the existing tests do not need to be modified. Required by the patch that fixes PR25722. Patch by Peter Smith. llvm-svn: 269353
* ARM: report an error when attempting to target a misalgined BLXTim Northover2016-05-102-0/+74
| | | | | | | The CodeGen problem was fixed in r269101, but we still miscompiled assembly that tried the same thing. llvm-svn: 269126
* Reapply: "ARM: put correct symbol index on indirect pointers in __thread_ptr.""Tim Northover2016-04-261-1/+5
| | | | | | | A latent bug in llvm-objdump used the wrong format specifier on 32-bit targets, causing the test to fail. This fixes the issue. llvm-svn: 267582
* Revert "ARM: put correct symbol index on indirect pointers in __thread_ptr."Renato Golin2016-04-261-5/+1
| | | | | | This reverts commit r267488, as it broke some ARM buildbots. llvm-svn: 267541
* ARM: put correct symbol index on indirect pointers in __thread_ptr.Tim Northover2016-04-251-1/+5
| | | | | | Otherwise the linker has no idea what should be resolved. llvm-svn: 267488
* ARM: put extern __thread stubs in a special section.Tim Northover2016-04-251-0/+46
| | | | | | | The linker needs to know that the symbols are thread-local to do its job properly. llvm-svn: 267473
* [LLVM] Remove unwanted --check-prefix=CHECK from unit tests. NFC.Mandeep Singh Grang2016-04-196-7/+7
| | | | | | | | | | | | Summary: Removed unwanted --check-prefix=CHECK from numerous unit tests. Reviewers: t.p.northover, dblaikie, uweigand, MatzeB, tstellarAMD, mcrosier Subscribers: mcrosier, dsanders Differential Revision: http://reviews.llvm.org/D19279 llvm-svn: 266834
* [PR27284] Reverse the ownership between DICompileUnit and DISubprogram.Adrian Prantl2016-04-151-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently each Function points to a DISubprogram and DISubprogram has a scope field. For member functions the scope is a DICompositeType. DIScopes point to the DICompileUnit to facilitate type uniquing. Distinct DISubprograms (with isDefinition: true) are not part of the type hierarchy and cannot be uniqued. This change removes the subprograms list from DICompileUnit and instead adds a pointer to the owning compile unit to distinct DISubprograms. This would make it easy for ThinLTO to strip unneeded DISubprograms and their transitively referenced debug info. Motivation ---------- Materializing DISubprograms is currently the most expensive operation when doing a ThinLTO build of clang. We want the DISubprogram to be stored in a separate Bitcode block (or the same block as the function body) so we can avoid having to expensively deserialize all DISubprograms together with the global metadata. If a function has been inlined into another subprogram we need to store a reference the block containing the inlined subprogram. Attached to https://llvm.org/bugs/show_bug.cgi?id=27284 is a python script that updates LLVM IR testcases to the new format. http://reviews.llvm.org/D19034 <rdar://problem/25256815> llvm-svn: 266446
* MCParser: diagnose missing directional labels more clearly.Tim Northover2016-04-111-3/+0
| | | | | | | | Before, ELF at least managed a diagnostic but it was a completely untraceable "undefined symbol" error. MachO had a variety of even worse behaviours: crash, emit corrupt file, or an equally bad message. llvm-svn: 265984
* [ARM] Avoid switching ARM/Thumb mode on .arch/.cpu directiveOliver Stannard2016-04-111-0/+52
| | | | | | | | | | | | | | | | | | | | When we see a .arch or .cpu directive, we should try to avoid switching ARM/Thumb mode if possible. If we do have to switch modes, we also need to emit the correct mapping symbol for the new ISA. We did not do this previously, so could emit ARM code with Thumb mapping symbols (or vice-versa). The GAS behaviour is to always stay in the same mode, and to emit an error on any instructions seen when the current mode is not available on the current target. We can't represent that situation easily (we assume that Thumb mode is available if ModeThumb is set), so we differ from the GAS behaviour when switching to a target that can't support the old mode. I've added a warning for when this implicit mode-switch occurs. Differential Revision: http://reviews.llvm.org/D18955 llvm-svn: 265936
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