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* Fix a bug in the type-legalization of vector integers. When we bitcast one ↵Nadav Rotem2012-01-181-0/+14
| | | | | | vector type to another, we must not bitcast the result if one type is widened while the other is promoted. llvm-svn: 148383
* Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.Nadav Rotem2012-01-173-5/+31
| | | | llvm-svn: 148337
* Fix 11769.Nadav Rotem2012-01-171-1/+12
| | | | | | | | In CanXFormVExtractWithShuffleIntoLoad we assumed that EXTRACT_VECTOR_ELT can be later handled by the DAGCombiner. However, in some cases on AVX, the EXTRACT_VECTOR_ELT is legalized to EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which currently is not handled by the DAGCombiner. In this patch I added a check that we only extract from the XMM part. llvm-svn: 148298
* AggressiveAntiDepBreaker needs to skip debug values because a debug value ↵Hal Finkel2012-01-161-0/+40
| | | | | | does not have a corresponding SUnit llvm-svn: 148260
* Make sure the non-SSE lowering for fences correctly clobbers EFLAGS. PR11768.Eli Friedman2012-01-161-0/+34
| | | | llvm-svn: 148240
* [AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits.Nadav Rotem2012-01-151-0/+37
| | | | | | | | | | | We know that the blend instructions only use the MSB, so if the mask is sign-extended then we can convert it into a SHL instruction. This is a common pattern because the type-legalizer sign-extends the i1 type which is used by the LLVM-IR for the condition. Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL. llvm-svn: 148225
* Relax the FileCheck assertion a bit -- all we really care about is thatChandler Carruth2012-01-151-1/+1
| | | | | | | we're loading from the global array, not how it is spelled in the asm. This should fix the MSVC bots. llvm-svn: 148214
* FileCheck-ize a test, make it more specific to directly test the shiftChandler Carruth2012-01-151-10/+14
| | | | | | removal desired. llvm-svn: 148213
* After r147827 and r147902, it's now possible for unallocatable registers to beEvan Cheng2012-01-141-0/+103
| | | | | | | | | | | | | | | | | | | live across BBs before register allocation. This miscompiled 197.parser when a cmp + b are optimized to a cbnz instruction even though the CPSR def is live-in a successor. cbnz r6, LBB89_12 ... LBB89_12: ble LBB89_1 The fix consists of two parts. 1) Teach LiveVariables that some unallocatable registers might be liveouts so don't mark their last use as kill if they are. 2) ARM constantpool island pass shouldn't form cbz / cbnz if the conditional branch does not kill CPSR. rdar://10676853 llvm-svn: 148168
* Cleanup test case by adding checks for test names.Chad Rosier2012-01-141-1/+2
| | | | llvm-svn: 148166
* Add a test showing how the Leh_func_endN symbol is used.Rafael Espindola2012-01-141-0/+27
| | | | llvm-svn: 148161
* test/CodeGen/ARM/test-sharedidx.ll: Fix for -Asserts.NAKAMURA Takumi2012-01-131-0/+1
| | | | llvm-svn: 148107
* Add patterns for v16i16 and v32i8 immAllZerosV to select VPXOR to match ↵Craig Topper2012-01-131-1/+1
| | | | | | v4i64 and v8i32. llvm-svn: 148106
* DAGCombine's logic for forming pre- and post- indexed loads / stores were beingEvan Cheng2012-01-132-4/+99
| | | | | | | | | | | | | | | | overly conservative. It was concerned about cases where it would prohibit folding simple [r, c] addressing modes. e.g. ldr r0, [r2] ldr r1, [r2, #4] => ldr r0, [r2], #4 ldr r1, [r2] Change the logic to look for such cases which allows it to form indexed memory ops more aggressively. rdar://10674430 llvm-svn: 148086
* Fixed a bug in LowerVECTOR_SHUFFLE caused assertion failureElena Demikhovsky2012-01-121-1/+9
| | | | | | | lc: X86ISelLowering.cpp:6480: llvm::SDValue llvm::X86TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `V1.getOpcode() != ISD::UNDEF&& "Op 1 of shuffle should not be undef"' failed. Added a test. llvm-svn: 148044
* Add error-reporting tests for platforms that don't support segmented stacks.Rafael Espindola2012-01-121-0/+11
| | | | | | Patch by Brian Anderson. llvm-svn: 148042
* Support segmented stacks on 64-bit FreeBSD.Rafael Espindola2012-01-121-0/+52
| | | | | | | This patch uses tcb_spare field in the tcb structure to store info. Patch by Jyun-Yan You. llvm-svn: 148041
* Support segmented stacks on win32.Rafael Espindola2012-01-121-0/+50
| | | | | | | Uses the pvArbitrary slot of the TIB, which is reserved for applications. We only support frames with a static size. llvm-svn: 148040
* Fix a bug in the AVX 256-bit shuffle code in cases where the splat element ↵Nadav Rotem2012-01-121-0/+12
| | | | | | | | is on the boundary of two 128-bit vectors. The attached testcase was stuck in an endless loop. llvm-svn: 148027
* X86: Generalize the x << (y & const) optimization to also catch masks with ↵Benjamin Kramer2012-01-121-3/+15
| | | | | | more set bits set than 31 or 63. llvm-svn: 148024
* On AVX, we can load v8i32 at a time. The bug happens when two uneven loads ↵Nadav Rotem2012-01-111-0/+12
| | | | | | | | | | are used. When we load the v12i32 type, the GenWidenVectorLoads method generates two loads: v8i32 and v4i32 and attempts to use CONCAT_VECTORS to join them. In this fix I concat undef values to widen the smaller value. The test "widen_load-2.ll" also exposes this bug on AVX. llvm-svn: 147964
* Check to make sure that the CFString's back store ends up in the correct ↵Bill Wendling2012-01-111-0/+36
| | | | | | section. llvm-svn: 147961
* Support segmented stacks on mac.Rafael Espindola2012-01-111-74/+205
| | | | | | | | This uses TLS slot 90, which actually belongs to JavaScriptCore. We only support frames with static size Patch by Brian Anderson. llvm-svn: 147960
* Split segmented stacks tests into tests for static- and dynamic-size frames.Rafael Espindola2012-01-112-37/+71
| | | | | | Patch by Brian Anderson. llvm-svn: 147959
* Generate the segmented stack prologue for fastcc too.Rafael Espindola2012-01-111-0/+55
| | | | | | Patch by Brian Anderson. llvm-svn: 147958
* Revert r147945 which disabled an addressing mode transformation. I hadChandler Carruth2012-01-111-10/+10
| | | | | | | | | hoped this would revive one of the llvm-gcc selfhost build bots, but it didn't so it doesn't appear that my transform is the culprit. If anyone else is seeing failures, please let me know! llvm-svn: 147957
* Use unsigned comparison in segmented stack prologue.Rafael Espindola2012-01-111-0/+6
| | | | | | | | This is a comparison of two addresses, and GCC does the comparison unsigned. Patch by Brian Anderson. llvm-svn: 147954
* Explicitly set the scale to 1 on some segstack prologue instrs.Rafael Espindola2012-01-111-0/+4
| | | | | | Patch by Brian Anderson. llvm-svn: 147952
* Add XOP Intrinsics and testsJan Sjödin2012-01-111-0/+1059
| | | | llvm-svn: 147949
* Fix a bug in the lowering of BUILD_VECTOR for AVX. SCALAR_TO_VECTOR does not ↵Nadav Rotem2012-01-112-5/+24
| | | | | | zero untouched elements. Use INSERT_VECTOR_ELT instead. llvm-svn: 147948
* Disable the transformation I added in r147936 to see if it fixes someChandler Carruth2012-01-111-10/+10
| | | | | | | | strange build bot failures that look like a miscompile into an infloop. I'll investigate this tomorrow, but I'd both like to know whether my patch is the culprit, and get the bots back to green. llvm-svn: 147945
* Fix undefined code and reenable test case.Jakob Stoklund Olesen2012-01-111-2/+1
| | | | | | | I don't think the compact encoding code is right, but at least is has defined behavior now. llvm-svn: 147938
* Teach the X86 instruction selection to do some heroic transforms toChandler Carruth2012-01-111-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | detect a pattern which can be implemented with a small 'shl' embedded in the addressing mode scale. This happens in real code as follows: unsigned x = my_accelerator_table[input >> 11]; Here we have some lookup table that we look into using the high bits of 'input'. Each entity in the table is 4-bytes, which means this implicitly gets turned into (once lowered out of a GEP): *(unsigned*)((char*)my_accelerator_table + ((input >> 11) << 2)); The shift right followed by a shift left is canonicalized to a smaller shift right and masking off the low bits. That hides the shift right which x86 has an addressing mode designed to support. We now detect masks of this form, and produce the longer shift right followed by the proper addressing mode. In addition to saving a (rather large) instruction, this also reduces stalls in Intel chips on benchmarks I've measured. In order for all of this to work, one part of the DAG needs to be canonicalized *still further* than it currently is. This involves removing pointless 'trunc' nodes between a zextload and a zext. Without that, we end up generating spurious masks and hiding the pattern. llvm-svn: 147936
* llvm/test/CodeGen/X86/zext-fold.ll: Relax an expression in stack offset.NAKAMURA Takumi2012-01-111-1/+1
| | | | llvm-svn: 147928
* llvm/test/CodeGen/X86/sub-with-overflow.ll: Add explicit -mtriple=i686-linux.NAKAMURA Takumi2012-01-111-1/+1
| | | | llvm-svn: 147927
* ARM Ld/St Optimizer fix.Andrew Trick2012-01-111-0/+46
| | | | | | | | Allow LDRD to be formed from pairs with different LDR encodings. This was the original intention of the pass. Somewhere along the way, the LDR opcodes were refined which broke the optimization. We really don't care what the original opcodes are as long as they both map to the same LDRD and the immediate still fits. Fixes rdar://10435045 ARMLoadStoreOptimization cannot handle mixed LDRi8/LDRi12 llvm-svn: 147922
* Disable test that seems to expose an unrelated Linux issue.Jakob Stoklund Olesen2012-01-111-1/+2
| | | | llvm-svn: 147921
* Detect when a value is undefined on an edge to a landing pad.Jakob Stoklund Olesen2012-01-111-0/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consider this code: int h() { int x; try { x = f(); g(); } catch (...) { return x+1; } return x; } The variable x is undefined on the first edge to the landing pad, but it has the f() return value on the second edge to the landing pad. SplitAnalysis::getLastSplitPoint() would assume that the return value from f() was live into the landing pad when f() throws, which is of course impossible. Detect these cases, and treat them as if the landing pad wasn't there. This allows spill code to be inserted after the function call to f(). <rdar://problem/10664933> llvm-svn: 147912
* Add test case for r147881.Chad Rosier2012-01-101-0/+19
| | | | llvm-svn: 147891
* Default stack alignment for 32bit x86 should be 4 Bytes, not 8 Bytes.Joerg Sonnenberger2012-01-101-0/+25
| | | | | | | Add a test that checks the stack alignment of a simple function for Darwin, Linux and NetBSD for 32bit and 64bit mode. llvm-svn: 147888
* Consider unknown alignment caused by OptimizeThumb2Instructions().Jakob Stoklund Olesen2012-01-101-0/+1400
| | | | | | | | | | | | | | | | | | | | This function runs after all constant islands have been placed, and may shrink some instructions to their 2-byte forms. This can actually cause some constant pool entries to move out of range because of growing alignment padding. Treat instructions that may be shrunk the same as inline asm - they erode the known alignment bits. Also reinstate an old assertion in verify(). It is correct now that basic block offsets include alignments. Add a single large test case that will hopefully exercise many parts of the constant island pass. <rdar://problem/10670199> llvm-svn: 147885
* ARM updating VST2 pseudo-lowering fixed vs. register update.Jim Grosbach2012-01-101-0/+9
| | | | | | rdar://10663487 llvm-svn: 147876
* Fix a bug in the legalization of shuffle vectors. When we emulate shuffles ↵Nadav Rotem2012-01-101-0/+13
| | | | | | using BUILD_VECTORS we may be using a BV of different type. Make sure to cast it back. llvm-svn: 147851
* Fix a crash in AVX2 when trying to broadcast a double into a 128-bit vector. ↵Craig Topper2012-01-102-0/+20
| | | | | | There is no vbroadcastsd xmm, but we do need to support 64-bit integers broadcasted into xmm. Also factor the AVX check into the isVectorBroadcast function. This makes more sense since the AVX2 check was already inside. llvm-svn: 147844
* Allow machine-cse to look across MBB boundary when cse'ing instructions thatEvan Cheng2012-01-103-3/+53
| | | | | | | | | | define physical registers. It's currently very restrictive, only catching cases where the CE is in an immediate (and only) predecessor. But it catches a surprising large number of cases. rdar://10660865 llvm-svn: 147827
* Cleanup and FileCheck-ize a test.Chandler Carruth2012-01-091-13/+25
| | | | llvm-svn: 147772
* Clean up patterns for MOVNT*. Not sure why there were floating point types ↵Craig Topper2012-01-091-0/+22
| | | | | | on MOVNTPS and MOVNTDQ. And v4i64 was completely missing. llvm-svn: 147767
* Don't print an unused label before .cfi_endproc.Rafael Espindola2012-01-093-5/+3
| | | | llvm-svn: 147763
* Don't disable MMX support when AVX is enabled. Fix predicates for MMX ↵Craig Topper2012-01-091-0/+1
| | | | | | instructions that were added along with SSE instructions to check for AVX in addition to SSE level. llvm-svn: 147762
* Reverted commit #147601 upon Evan's request.Victor Umansky2012-01-082-486/+0
| | | | llvm-svn: 147748
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