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* Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.Evan Cheng2011-01-173-4/+4
| | | | | | | | | | | | movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4)) movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4)) LPC0_0: add r0, pc, r0 It's not yet enabled by default as some tests are failing. I suspect bugs in down stream tools. llvm-svn: 123619
* Update tests.Rafael Espindola2011-01-166-22/+22
| | | | llvm-svn: 123591
* fix PR8514, a bug where the "heroic" transformation of shift/and Chris Lattner2011-01-161-0/+36
| | | | | | | | into and/shift would cause nodes to move around and a dangling pointer to happen. The code tried to avoid this with a HandleSDNode, but got the details wrong. llvm-svn: 123578
* Spill R4 if it's going to be used to restore SP from FP.Evan Cheng2011-01-161-0/+17
| | | | llvm-svn: 123567
* Implement AnalyzeBranch in Sparc Backend.Venkatraman Govindaraju2011-01-161-7/+7
| | | | llvm-svn: 123561
* fix PR8981, a crash trying to form a conditional inc with a floating point ↵Chris Lattner2011-01-161-0/+10
| | | | | | compare. llvm-svn: 123560
* reapply my fix for PR8961 with a tweak to properly handleChris Lattner2011-01-161-0/+17
| | | | | | | multi-instruction sequences like calls. Many thanks to Jakob for finding a testcase. llvm-svn: 123559
* revert my fastisel patch again which apparently still gives theChris Lattner2011-01-141-17/+0
| | | | | | llvm-gcc-i386-linux-selfhost buildbot heartburn... llvm-svn: 123431
* reapply r123414 now that the botz are calmed down and the fix is already in.Chris Lattner2011-01-141-0/+17
| | | | llvm-svn: 123427
* r123414 broke llvm-gcc bootstrap apparently, revertChris Lattner2011-01-141-17/+0
| | | | llvm-svn: 123422
* fix PR8961 - a fast isel miscompilation where we'd insert a new instructionChris Lattner2011-01-141-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | after sext's generated for addressing that got folded. Previously we compiled test5 into: _test5: ## @test5 ## BB#0: movq -8(%rsp), %rax ## 8-byte Reload movq (%rdi,%rax), %rdi addq %rdx, %rdi movslq %esi, %rax movq %rax, -8(%rsp) ## 8-byte Spill movq %rdi, %rax ret which is insane and wrong. Now we produce: _test5: ## @test5 ## BB#0: movslq %esi, %rax movq (%rdi,%rax), %rax addq %rdx, %rax ret llvm-svn: 123414
* Experiment with changing the default 32-bit linux stack alignment toEric Christopher2011-01-135-62/+80
| | | | | | 16 bytes for PR8969. Update all testcases accordingly. llvm-svn: 123367
* Try again enabling LiveDebugVariables.Jakob Stoklund Olesen2011-01-123-5/+4
| | | | llvm-svn: 123342
* Implement RETURNADDR and FRAMEADDR lowering in SPARC backend.Venkatraman Govindaraju2011-01-121-0/+46
| | | | llvm-svn: 123310
* Fix SPARC backend call instruction so that arguments passed through registersVenkatraman Govindaraju2011-01-121-0/+13
| | | | | | | are correctly marked as used instead of passing all possible argument registers as used. llvm-svn: 123301
* The world is not ready for LiveDebugVariables yet.Jakob Stoklund Olesen2011-01-113-4/+5
| | | | llvm-svn: 123290
* Enable LiveDebugVariables by default.Jakob Stoklund Olesen2011-01-113-5/+4
| | | | llvm-svn: 123282
* SPARC backend: correct ICC/FCC uses for ADDX and SELECT_CCVenkatraman Govindaraju2011-01-111-0/+76
| | | | llvm-svn: 123281
* Even if we don't have 7 bytes of stack space we may need to save andEric Christopher2011-01-111-0/+40
| | | | | | | | restore the stack pointer from the frame pointer on thumbv6. Fixes rdar://8819685 llvm-svn: 123196
* Fix PR 8916 (qv for analysis), at least the immediate problem.Dale Johannesen2011-01-101-0/+15
| | | | | | | | | | | There's an inherent tension in DAGCombine between assuming that things will be put in canonical form, and the Depth mechanism that disables transformations when recursion gets too deep. It would not surprise me if there's a lot of little bugs like this one waiting to be discovered. The mechanism seems fragile and I'd suggest looking at it from a design viewpoint. llvm-svn: 123191
* Recognize inline asm 'rev /bin/bash, ' as a bswap intrinsic call.Evan Cheng2011-01-082-2/+11
| | | | llvm-svn: 123048
* Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng2011-01-071-7/+9
| | | | | | | | | | Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. llvm-svn: 123044
* Speculatively revert r123032.Devang Patel2011-01-073-2/+4
| | | | llvm-svn: 123039
* Lower some BUILD_VECTORS using VEXT+shuffle.Bob Wilson2011-01-071-0/+59
| | | | | | Patch by Tim Northover. llvm-svn: 123035
* Appropriately truncate debug info range in dwarf output.Devang Patel2011-01-073-3/+58
| | | | | | Enable live debug variables pass. llvm-svn: 123032
* Revert r122955. It seems using movups to lower memcpy can cause massive ↵Evan Cheng2011-01-0710-78/+96
| | | | | | regression (even on Nehalem) in edge cases. I also didn't see any real performance benefit. llvm-svn: 123015
* Try to unbreak the arm buildbot.Benjamin Kramer2011-01-071-1/+1
| | | | llvm-svn: 122999
* Add testcases for PR8411 (vget_low and vget_high implemented as shuffles).Bob Wilson2011-01-071-1/+37
| | | | llvm-svn: 122997
* Add ARM patterns to match EXTRACT_SUBVECTOR nodes.Bob Wilson2011-01-072-2/+8
| | | | | | | | | | | | | | | Also fix an off-by-one in SelectionDAGBuilder that was preventing shuffle vectors from being translated to EXTRACT_SUBVECTOR. Patch by Tim Northover. The test changes are needed to keep those spill-q tests from testing aligned spills and restores. If the only aligned stack objects are spill slots, we no longer realign the stack frame. Prior to this patch, an EXTRACT_SUBVECTOR was legalized by loading from the stack, which created an aligned frame index. Now, however, there is nothing except the spill slot in the stack frame, so I added an aligned alloca. llvm-svn: 122995
* Fix the other problem reported in PR8582. Testcase and patch byDuncan Sands2011-01-061-0/+19
| | | | | | Nadav Rotem. llvm-svn: 122983
* Add a testcase for PR8582, which mysteriously fixed itself, in case the problemDuncan Sands2011-01-061-0/+15
| | | | | | comes back some day. llvm-svn: 122982
* PR8921: LDM/POP do not support interworking prior to v5t.Bob Wilson2011-01-067-17/+26
| | | | llvm-svn: 122970
* Use movups to lower memcpy and memset even if it's not fast (like corei7).Evan Cheng2011-01-0610-96/+78
| | | | | | | | The theory is it's still faster than a pair of movq / a quad of movl. This will probably hurt older chips like P4 but should run faster on current and future Intel processors. rdar://8817010 llvm-svn: 122955
* Re-implement r122936 with proper target hooks. Now getMaxStoresPerMemcpyEvan Cheng2011-01-062-24/+48
| | | | | | | etc. takes an option OptSize. If OptSize is true, it would return the inline limit for functions with attribute OptSize. llvm-svn: 122952
* Revert r122936. I'll re-implement the change.Evan Cheng2011-01-062-48/+24
| | | | llvm-svn: 122949
* Fix test to coincide with r122934 change from PR8919.Bill Wendling2011-01-061-1/+1
| | | | llvm-svn: 122937
* r105228 reduced the memcpy / memset inline limit to 4 with -Os to avoid blowingEvan Cheng2011-01-062-24/+48
| | | | | | | | up freebsd bootloader. However, this doesn't make much sense for Darwin, whose -Os is meant to optimize for size only if it doesn't hurt performance. rdar://8821501 llvm-svn: 122936
* Avoid zero extend bit test operands to pointer type if all the masks fit inEvan Cheng2011-01-061-0/+30
| | | | | | | the original type of the switch statement key. rdar://8781238 llvm-svn: 122935
* Optimize:Evan Cheng2011-01-051-0/+60
| | | | | | | | | r1025 = s/zext r1024, 4 r1026 = extract_subreg r1025, 4 to: r1026 = copy r1024 llvm-svn: 122925
* fix PR8900, a shuffle miscompilation. Patch by Nadav Rotem!Chris Lattner2011-01-051-0/+13
| | | | llvm-svn: 122921
* Use pushq / popq instead of subq $8, %rsp / addq $8, %rsp to adjust stack inEvan Cheng2011-01-037-170/+170
| | | | | | | | | | | prologue and epilogue if the adjustment is 8. Similarly, use pushl / popl if the adjustment is 4 in 32-bit mode. In the epilogue, takes care to pop to a caller-saved register that's not live at the exit (either return or tailcall instruction). rdar://8771137 llvm-svn: 122783
* Try to reuse the value when lowering memset.Benjamin Kramer2011-01-021-0/+9
| | | | | | | | | | This allows us to compile: void test(char *s, int a) { __builtin_memset(s, a, 15); } into 1 mul + 3 stores instead of 3 muls + 3 stores. llvm-svn: 122710
* Lower the i8 extension in memset to a multiply instead of a potentially long ↵Benjamin Kramer2011-01-021-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | series of shifts and ors. We could implement a DAGCombine to turn x * 0x0101 back into logic operations on targets that doesn't support the multiply or it is slow (p4) if someone cares enough. Example code: void test(char *s, int a) { __builtin_memset(s, a, 4); } before: _test: ## @test movzbl 8(%esp), %eax movl %eax, %ecx shll $8, %ecx orl %eax, %ecx movl %ecx, %eax shll $16, %eax orl %ecx, %eax movl 4(%esp), %ecx movl %eax, 4(%ecx) movl %eax, (%ecx) ret after: _test: ## @test movzbl 8(%esp), %eax imull $16843009, %eax, %eax ## imm = 0x1010101 movl 4(%esp), %ecx movl %eax, 4(%ecx) movl %eax, (%ecx) ret llvm-svn: 122707
* Fix darwin bots.Rafael Espindola2011-01-011-1/+1
| | | | llvm-svn: 122672
* Add support for the 'H' modifier.Rafael Espindola2011-01-011-0/+12
| | | | llvm-svn: 122667
* Update the testAnton Korobeynikov2011-01-011-1/+1
| | | | llvm-svn: 122666
* ptx: remove reg-reg addressing mode and st.constChe-Liang Chiou2011-01-012-10/+4
| | | | llvm-svn: 122653
* ptx: add store instructionChe-Liang Chiou2011-01-011-0/+78
| | | | llvm-svn: 122652
* ptx: add state spacesChe-Liang Chiou2010-12-301-1/+34
| | | | llvm-svn: 122638
* test/CodeGen/X86/negative-sin.ll: FileCheck-ize.NAKAMURA Takumi2010-12-291-2/+2
| | | | llvm-svn: 122619
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