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* [ARM] Make RWPI use movw/movt when availableChristof Douma2017-02-071-19/+125
| | | | | | | | | | | | | | | | | When constructing global address literals while targeting the RWPI relocation model. LLVM currently only uses literal pools. If MOVW/MOVT instructions are available we can use these instead. Beside being more efficient it allows -arm-execute-only to work with -relocation-model=RWPI as well. When we generate MOVW/MOVT for global addresses when targeting the RWPI relocation model, we need to use base relative relocations. This patch does the needed plumbing in MC to generate these for MOVW/MOVT. Differential Revision: https://reviews.llvm.org/D29487 Change-Id: I446786e43a6f5aa9b6a5bb2cd216d60d41c7755d llvm-svn: 294298
* [X86][SSE] Added 256-bit vector tests casesSimon Pilgrim2017-02-071-0/+1151
| | | | | | Exposes some poor codegen with identity shuffle due to bad interaction with insert_subvector(extract_subvector) / concat_subvectors llvm-svn: 294296
* Revert "[DAGCombiner] (add X, (adde Y, 0, Carry)) -> (adde X, Y, Carry)"Daniel Jasper2017-02-071-6/+7
| | | | | | | | | | | | | This reverts commit r294186. On an internal test, this triggers an out-of-memory error on PPC, presumably because there is another dagcombine that does the exact opposite triggering and endless loop consuming more and more memory. Chandler has started at creating a reduced test case and we'll attach it as soon as possible. llvm-svn: 294288
* [AVX-512] Add masked and unmasked shift by immediate instructions to load ↵Craig Topper2017-02-071-0/+102
| | | | | | folding tables. llvm-svn: 294287
* [AVX-512] Add masked shift instructions to load folding tables.Craig Topper2017-02-071-0/+42
| | | | | | This adds the masked versions of everything, but the shift by immediate instructions. llvm-svn: 294286
* [AVX-512] Add some of the shift instructions to the load folding tables.Craig Topper2017-02-072-0/+486
| | | | | | | | This includes unmasked forms of variable shift and shifting by the lower element of a register. Still need to do shift by immediate which was not foldable prior to avx512 and all the masked forms. llvm-svn: 294285
* [X86] Change the Defs list for VZEROALL/VZEROUPPER back to not including ↵Craig Topper2017-02-071-14/+28
| | | | | | YMM16-31. llvm-svn: 294277
* [AVX-512] Put the integer stack folding tests in alphabetical order.Craig Topper2017-02-072-1253/+1237
| | | | llvm-svn: 294276
* RegisterCoalescer: Fix joinReservedPhysReg()Matthias Braun2017-02-071-20/+75
| | | | | | | | | | | joinReservedPhysReg() can only deal with a liverange in a single basic block when copying from a vreg into a physreg. See also rdar://30306405 Differential Revision: https://reviews.llvm.org/D29436 llvm-svn: 294268
* [AMDGPU] Lower null pointers in static variable initializerYaxun Liu2017-02-071-0/+113
| | | | | | | | | | | | For amdgcn target Clang generates addrspacecast to represent null pointers in private and local address spaces. In LLVM codegen, the static variable initializer is lowered by virtual function AsmPrinter::lowerConstant which is target generic. Since addrspacecast is target specific, AsmPrinter::lowerConst This patch overrides AsmPrinter::lowerConstant with AMDGPUAsmPrinter::lowerConstant, which is able to lower the target-specific addrspacecast in the null pointer representation so that -1 is co Differential Revision: https://reviews.llvm.org/D29284 llvm-svn: 294265
* [x86] add tests to show current codegen for vblendv*; NFCSanjay Patel2017-02-071-0/+319
| | | | | | | As noted in the comments, we should be able to eliminate cmp ops in several cases. llvm-svn: 294263
* GlobalISel: legalize narrow G_SELECTS on AArch64.Tim Northover2017-02-061-5/+15
| | | | | | Otherwise there aren't any patterns to select them. llvm-svn: 294261
* [Hexagon] Adding gp+ to the syntax of gp-relative instructionsKrzysztof Parzyszek2017-02-064-12/+12
| | | | | | Patch by Colin LeMahieu. llvm-svn: 294258
* [X86][SSE] Tests showing the lowering of float/double complex ↵Simon Pilgrim2017-02-061-0/+215
| | | | | | multiplications with fastmath (PR31866) llvm-svn: 294254
* GlobalISel: fall back gracefully when we can't map an operand's size.Tim Northover2017-02-061-0/+8
| | | | | | | | AArch64 was asserting when it was asked to provide a register-bank of a size it couldn't deal with (in this case an s128 IMPLICIT_DEF). But we want a robust fallback path so this isn't allowed. llvm-svn: 294248
* GlobalISel: legalize G_INSERT instructionsTim Northover2017-02-062-2/+102
| | | | | | | We don't handle all cases yet (see arm64-fallback.ll for an example), but this is enough to cover most common C++ code so it's a good place to start. llvm-svn: 294247
* [X86][SSE] Add tests showing missed opportunities to simplify integer ↵Simon Pilgrim2017-02-061-0/+79
| | | | | | absolute instructions llvm-svn: 294216
* [AArch64] Fix incorrect MachinePointerInfo in splitStoreSplatJohn Brawn2017-02-062-0/+131
| | | | | | | | | | | When splitting up one store into several in splitStoreSplat we have to make sure we get the MachinePointerInfo right, otherwise alias analysis thinks they all store to the same location. This can then cause invalid scheduling later on. Differential Revision: https://reviews.llvm.org/D29446 llvm-svn: 294203
* [DAGCombiner] Support bswap as a part of load combine patternsArtur Pilipenko2017-02-065-0/+145
| | | | | | | | Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D29397 llvm-svn: 294201
* Commit full codegen for mul-i256.ll . NFCAmaury Sechet2017-02-061-19/+277
| | | | | | The full codegen is committed for larger multiply, so that won't make the test suite more fragile. However, it'll allow to expose the effects fo various DAG combine. llvm-svn: 294196
* Add ADDC to SelectionDAG::computeKnownBits and ComputeNumSignBits.Amaury Sechet2017-02-061-4/+2
| | | | | | | | | | | | Summary: As per title. Reviewers: bkramer, sunfish, lattner, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29521 llvm-svn: 294188
* [DAGCombiner] Make DAGCombiner smarter about overflowAmaury Sechet2017-02-061-2/+1
| | | | | | | | | | | | Summary: Leverage it to transform addc into add. Reviewers: mkuper, spatel, RKSimon, zvi Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29524 llvm-svn: 294187
* [DAGCombiner] (add X, (adde Y, 0, Carry)) -> (adde X, Y, Carry)Amaury Sechet2017-02-061-7/+6
| | | | | | | | | | | | Summary: This is extracted from D29443 . Reviewers: mkuper, spatel, RKSimon, zvi, bkramer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29564 llvm-svn: 294186
* Add DAGCombiner load combine tests with non-zero offsetArtur Pilipenko2017-02-065-3/+805
| | | | | | This is separated from https://reviews.llvm.org/D29394 review. llvm-svn: 294185
* [X86] Add add/addc known-bits tests (D29521)Simon Pilgrim2017-02-061-0/+66
| | | | llvm-svn: 294184
* [X86][SSE] Combine shuffle nodes with multiple uses if all the users are ↵Simon Pilgrim2017-02-064-43/+8
| | | | | | | | | | | | | | being combined. Currently we only combine shuffle nodes if they have a single user to prevent us from causing code bloat by splitting the shuffles into several different combines. We don't take into account that in some cases we will already have combined all the users during recursively calling up the shuffle tree. This patch keeps a list of all the shuffle nodes that have been combined so far and permits combining of further shuffle nodes if all its users are in that list. Differential Revision: https://reviews.llvm.org/D29399 llvm-svn: 294183
* [X86][GlobalISel] Add limited ret lowering support to the IRTranslator.Igor Breger2017-02-062-38/+181
| | | | | | | | | | | | | | | | Summary: Support return lowering for i8/i16/i32/i64/float/double, vector type supported for 64bit platform only. Support argument lowering for float/double types. Reviewers: t.p.northover, zvi, ab, rovka Reviewed By: zvi Subscribers: dberris, kristof.beyls, delena, llvm-commits Differential Revision: https://reviews.llvm.org/D29261 llvm-svn: 294173
* [AVX-512] Add VPSLLDQ/VPSRLDQ to load folding tables.Craig Topper2017-02-062-0/+48
| | | | llvm-svn: 294170
* [AVX-512] Add VPABSB/D/Q/W to load folding tables.Craig Topper2017-02-062-0/+172
| | | | llvm-svn: 294169
* [AVX-512] Add VSHUFPS/PD to load folding tables.Craig Topper2017-02-061-0/+39
| | | | llvm-svn: 294168
* [AVX-512] Add all masked and unmasked versions of VPMULDQ and VPMULUDQ to ↵Craig Topper2017-02-051-0/+59
| | | | | | load folding tables. llvm-svn: 294163
* [X86][SSE] Replace insert_vector_elt(vec, -1, idx) with shuffleSimon Pilgrim2017-02-051-22/+12
| | | | | | Similar to what we already do for zero elt insertion, we can quickly rematerialize 'allbits' vectors so to avoid a unnecessary gpr value and insertion into a vector llvm-svn: 294162
* [AVX-512] Add scalar masked max/min intrinsic instructions to the load ↵Craig Topper2017-02-051-0/+62
| | | | | | folding tables. llvm-svn: 294153
* [AVX-512] Add scalar masked add/sub/mul/div intrinsic instructions to the ↵Craig Topper2017-02-051-0/+62
| | | | | | load folding tables. llvm-svn: 294152
* [AVX-512] Add masked scalar FMA intrinsics to ↵Craig Topper2017-02-051-8/+4
| | | | | | isNonFoldablePartialRegisterLoad to improve load folding of scalar loads. llvm-svn: 294151
* [AVX-512] Add test cases that show failure to fold scalar loads into masked ↵Craig Topper2017-02-051-0/+108
| | | | | | scalar FMA intrinsics. llvm-svn: 294150
* [AVX-512] Move 128/256-bit intrinsic tests from avx512bwvl test file to ↵Craig Topper2017-02-052-1111/+1112
| | | | | | avx512vl test file. llvm-svn: 294149
* [X86][AVX] Add 8i32 -> 8f32 sitofp tests with constant insertionSimon Pilgrim2017-02-051-0/+158
| | | | | | Some elements are constant inserted into the source integer vector before conversion. llvm-svn: 294147
* [AVR] Implement stacksave/stackrestore by expanding (PR31342)Dylan McKay2017-02-051-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Authored by Florian Zeitz. This implements the missing stacksave/stackrestore intrinsics via expansion. Output of `llc -O0 -march=avr ~/devel/llvm/test/CodeGen/Generic/stacksave-restore.ll` for sanity checking (comments mine): ``` .text .file ".../llvm/test/CodeGen/Generic/stacksave-restore.ll" .globl test .p2align 1 .type test,@function test: ; @test ; BB#0: push r28 push r29 in r28, 61 in r29, 62 sbiw r28, 4 in r0, 63 cli out 62, r29 out 63, r0 out 61, r28 in r18, 61 in r19, 62 mov r20, r22 mov r21, r23 in r30, 61 in r31, 62 lsl r22 rol r23 lsl r22 rol r23 in r26, 61 in r27, 62 sub r26, r22 sbc r27, r23 andi r26, 252 in r0, 63 cli out 62, r27 out 63, r0 out 61, r26 in r0, 63 cli out 62, r31 out 63, r0 out 61, r30 in r30, 61 in r31, 62 sub r30, r22 sbc r31, r23 andi r30, 252 in r0, 63 cli out 62, r31 out 63, r0 out 61, r30 std Y+3, r24 ; 2-byte Folded Spill std Y+4, r25 ; 2-byte Folded Spill mov r24, r26 mov r25, r27 in r0, 63 cli out 62, r19 out 63, r0 out 61, r18 std Y+1, r20 ; 2-byte Folded Spill std Y+2, r21 ; 2-byte Folded Spill adiw r28, 4 in r0, 63 cli out 62, r29 out 63, r0 out 61, r28 pop r29 pop r28 ret .Lfunc_end0: .size test, .Lfunc_end0-test ``` Reviewers: dylanmckay Reviewed By: dylanmckay Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29553 llvm-svn: 294146
* [AVR] Marm MIR test functions as tracking liveness informationDylan McKay2017-02-053-2/+5
| | | | | | This fixes an assertion error that broke three tests. llvm-svn: 294140
* [X86] Fix printing of sha256rnds2 to include the implicit %xmm0 argument.Craig Topper2017-02-051-3/+3
| | | | llvm-svn: 294132
* [X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit ↵Craig Topper2017-02-0521-276/+276
| | | | | | %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
* [X86] In LowerTRUNCATE, create an ISD::VECTOR_SHUFFLE instead of explicitly ↵Craig Topper2017-02-0514-90/+90
| | | | | | | | | | | | creating a PSHUFB. This will be lowered by regular shuffle lowering to a PSHUFB later. Similar was already done for several other shuffles in this function. The test changes are because the old code used explicity zeroing for elements that could have been undef. While I was here I also changed other shuffle vectors in the same function to use the same input twice instead of creating UNDEF nodes. getVectorShuffle can create the UNDEF for us. llvm-svn: 294130
* [SelectionDAG] In InstrEmitter, handle EXTRACT_SUBREG of a physical register.Geoff Berry2017-02-051-23/+76
| | | | | | | | | | | | | | | | | | | Summary: Without this change, the getVR() call would hit an assert since it was being passed a physical register. Update the AArch64/ldst-opt.ll test with a case that triggers this behavior by adding a run with strict-align, which causes an unaligned STR XZR instruction to be split into byte stores, creating an EXTRACT_SUBREG of XZR that triggers the original problem. Reviewers: bogner, qcolombet, MatzeB, atrick Subscribers: aemerson, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D29495 llvm-svn: 294129
* [X86][SSE] Add target cpu specific reciprocal testsSimon Pilgrim2017-02-052-166/+915
| | | | | | As discussed on D26855, check individual cpu targets as part of the investigation into moving more combines to MachineCombiner llvm-svn: 294128
* [DAGCombiner] Leverage add's commutativityAmaury Sechet2017-02-051-11/+7
| | | | | | | | | | | | Summary: This avoid the need to duplicate all pattern and actually end up exposing some opportunity to optimize existing pattern that did not exists in both directions on an existing test case. Reviewers: mkuper, spatel, bkramer, RKSimon, zvi Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29541 llvm-svn: 294125
* [AVR] Fix a bug where asm operands are printed twiceDylan McKay2017-02-051-0/+8
| | | | | | | We would unconditionally call printOperand, even if PrintAsmOperand already printed the immediate. llvm-svn: 294121
* [X86] Add support for folding (insert_subvector vec1, (extract_subvector ↵Craig Topper2017-02-043-6/+3
| | | | | | vec2, idx1), idx1) -> (blendi vec2, vec1). llvm-svn: 294112
* [DAGCombiner] Canonicalize the order of a chain of INSERT_SUBVECTORs.Craig Topper2017-02-041-18/+16
| | | | | | Based on similar code for INSERT_VECTOR_ELT. llvm-svn: 294110
* Add test cases for (trunc adde) DAGCombiner patterns. NFCAmaury Sechet2017-02-041-0/+63
| | | | llvm-svn: 294105
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