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* Fix this test - there don't appear to be any actual Reload ReusesDan Gohman2009-11-161-1/+0
| | | | | | in this testcase. llvm-svn: 88998
* Revert r87049, which was the workaround for the regression triggeredDan Gohman2009-11-161-2/+2
| | | | | | | by the recent FixedStackPseudoSourceValue-related changes, now that the specific bug that affected it is fixed, in r88954. llvm-svn: 88997
* Convert to FileCheckJim Grosbach2009-11-161-5/+18
| | | | llvm-svn: 88991
* - Check memoperand alignment instead of checking stack alignment. Most load ↵Evan Cheng2009-11-161-0/+28
| | | | | | | | / store folding instructions are not referencing spill stack slots. - Mark MOVUPSrm re-materializable. llvm-svn: 88974
* Convert to FileCheckJim Grosbach2009-11-161-5/+17
| | | | llvm-svn: 88947
* Added a testcase for PR5495.Lang Hames2009-11-161-0/+75
| | | | llvm-svn: 88946
* Convert to FileCheckJim Grosbach2009-11-161-3/+7
| | | | llvm-svn: 88942
* tbb opt off by defaultJim Grosbach2009-11-161-0/+1
| | | | llvm-svn: 88921
* Support spill comments.David Greene2009-11-161-0/+105
| | | | | | | | Have the asm printer emit a comment if an instruction is a spill or reload and have the spiller mark copies it introdues so the asm printer can also annotate those. llvm-svn: 88911
* Check if subreg index is zero.Evan Cheng2009-11-161-0/+155
| | | | llvm-svn: 88899
* For some targets, a copy can use a register multiple times, e.g. ppc.Evan Cheng2009-11-161-0/+105
| | | | llvm-svn: 88895
* xfail for now. It has been failing.Evan Cheng2009-11-161-0/+1
| | | | llvm-svn: 88892
* - Fix a small bug while handling target constant pools (one param was missing).Bruno Cardoso Lopes2009-11-161-0/+10
| | | | | | | | | | | | | | | - Add a smarter constant pool loading, instead of: lui $2, %hi($CPI1_0) addiu $2, $2, %lo($CPI1_0) lwc1 $f0, 0($2) Generate: lui $2, %hi($CPI1_0) lwc1 $f0, %lo($CPI1_0)($2) llvm-svn: 88886
* Detect need for autoalignment of the stack earlier to catch spills moreJim Grosbach2009-11-152-4/+6
| | | | | | | conservatively. eliminateFrameIndex() machinery adjust to handle addr mode 6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling llvm-svn: 88874
* remove xfailJim Grosbach2009-11-141-2/+0
| | | | llvm-svn: 88817
* Add XCore support for arbitrary-sized aggregate returns.Richard Osborne2009-11-141-0/+43
| | | | llvm-svn: 88802
* Added getSubRegIndex(A,B) that returns subreg index of A to B. Use it to ↵Evan Cheng2009-11-141-0/+133
| | | | | | replace broken code in VirtRegRewriter. llvm-svn: 88753
* - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.Evan Cheng2009-11-141-1/+2
| | | | | | | | - If destination is a physical register and it has a subreg index, use the sub-register instead. This fixes PR5423. llvm-svn: 88745
* Add radar number.Evan Cheng2009-11-141-0/+1
| | | | llvm-svn: 88739
* Fix PR5412: Fix an inverted check and another missing sub-register check.Evan Cheng2009-11-142-0/+235
| | | | llvm-svn: 88738
* Enable the tail call optimization when the caller returns undef.Dan Gohman2009-11-141-1/+8
| | | | llvm-svn: 88737
* When expanding t2STRDi8 r, r to two stores, add kill markers correctly.Evan Cheng2009-11-141-0/+20
| | | | llvm-svn: 88734
* Fix PR5411. Bug in UpdateKills. A reg def partially define its super-registers.Evan Cheng2009-11-131-0/+42
| | | | llvm-svn: 88719
* When optimizing for size, don't tail-merge unless it's likely to be aDan Gohman2009-11-131-0/+113
| | | | | | | | | | code-size win, and not when it's only likely to be code-size neutral, such as when only a single instruction would be eliminated and a new branch would be required. This fixes rdar://7392894. llvm-svn: 88692
* Fix PR5410: LiveVariables lost subreg def:Evan Cheng2009-11-131-0/+20
| | | | | | | | | | | | | | D0<def,dead> = ... ... = S0<use, kill> S0<def> = ... ... D0<def> = The first D0 def is correctly marked dead, however, livevariables should have added an implicit def of S0 or we end up with a use without a def. llvm-svn: 88690
* Don't let a noalias difference disrupt the tailcall optimization.Dan Gohman2009-11-131-1/+15
| | | | llvm-svn: 88672
* Adjust isConstantSplat to allow for big-endian targets.Dale Johannesen2009-11-131-0/+24
| | | | | | PPC is such a target; make it work. llvm-svn: 87060
* Update test.Daniel Dunbar2009-11-131-2/+2
| | | | llvm-svn: 87049
* Clean up testcase a bit. Simplify case blocks and adjust switch instruction ↵Jim Grosbach2009-11-121-7/+3
| | | | | | to not take an undefined value as input. llvm-svn: 86997
* Fix typo in run line.Benjamin Kramer2009-11-121-1/+1
| | | | llvm-svn: 86984
* RegScavenger::enterBasicBlock should always reset register state.Evan Cheng2009-11-121-0/+85
| | | | llvm-svn: 86972
* - Teach LSR to avoid changing cmp iv stride if it will create an immediate thatEvan Cheng2009-11-121-0/+37
| | | | | | | | | | | | | | cannot be folded into target cmp instruction. - Avoid a phase ordering issue where early cmp optimization would prevent the later count-to-zero optimization. - Add missing checks which could cause LSR to reuse stride that does not have users. - Fix a bug in count-to-zero optimization code which failed to find the pre-inc iv's phi node. - Remove, tighten, loosen some incorrect checks disable valid transformations. - Quite a bit of code clean up. llvm-svn: 86969
* Tail merge at any size when there are two potentials blocks and oneDan Gohman2009-11-121-0/+27
| | | | | | can be made to fall through into the other. llvm-svn: 86909
* x86 users can now return arbitrary sized structs. Structs too large to fit ↵Kenneth Uildriks2009-11-111-0/+17
| | | | | | in return registers will be returned through a hidden sret parameter introduced during SelectionDAG construction. llvm-svn: 86876
* Add support for tail duplication to BranchFolding, and extendDan Gohman2009-11-114-7/+276
| | | | | | | | | | | tail merging support to handle more cases. - Recognize several cases where tail merging is beneficial even when the tail size is smaller than the generic threshold. - Make use of MachineInstrDesc::isBarrier to help detect non-fallthrough blocks. - Check for and avoid disrupting fall-through edges in more cases. llvm-svn: 86871
* Add nounwind.Evan Cheng2009-11-114-4/+4
| | | | llvm-svn: 86814
* Fix test to work on every platform.Bill Wendling2009-11-111-3/+1
| | | | llvm-svn: 86786
* Fix test to work on every platform.Bill Wendling2009-11-111-1/+1
| | | | llvm-svn: 86785
* Make sure that the exception handling data has the same visibility as theBill Wendling2009-11-111-0/+30
| | | | | | function it's generated for. llvm-svn: 86779
* Test this on Darwin only.Bill Wendling2009-11-101-0/+2
| | | | llvm-svn: 86752
* Emit correct code when making a ConstantPool entry for a vectorDale Johannesen2009-11-101-0/+36
| | | | | | | | | constant whose component type is not a legal type for the target. (If the target ConstantPool cannot handle this type either, it has an opportunity to merge elements. In practice any target with 8-bit bytes must support i8 *as data*). 7320806 (partial). llvm-svn: 86751
* Modify how the prologue encoded the "move" information for the FDE. GCCBill Wendling2009-11-101-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | generates a sequence similar to this: __Z4funci: LFB2: mflr r0 LCFI0: stmw r30,-8(r1) LCFI1: stw r0,8(r1) LCFI2: stwu r1,-80(r1) LCFI3: mr r30,r1 LCFI4: where LCFI3 and LCFI4 are used by the FDE to indicate what the FP, LR, and other things are. We generated something more like this: Leh_func_begin1: mflr r0 stw r31, 20(r1) stw r0, 8(r1) Llabel1: stwu r1, -80(r1) Llabel2: mr r31, r1 Note that we are missing the "mr" instruction. This patch makes it more like the GCC output. llvm-svn: 86729
* Add testcase for recent checkin.Mike Stump2009-11-091-0/+55
| | | | llvm-svn: 86620
* Update testJim Grosbach2009-11-091-1/+1
| | | | llvm-svn: 86614
* Use Unified Assembly Syntax for the ARM backend.Jim Grosbach2009-11-0936-117/+120
| | | | llvm-svn: 86494
* Add and-not (bic) patterns. Based heavily on patch by Brian Lucas!Anton Korobeynikov2009-11-086-2/+54
| | | | llvm-svn: 86471
* Fix invalid operand updates & implement post-inc memory operandsAnton Korobeynikov2009-11-081-1/+90
| | | | llvm-svn: 86466
* It is invalid to infer the value type from the result #0 of the nodeAnton Korobeynikov2009-11-081-0/+64
| | | | | | since the instruction might use the other result of different type. llvm-svn: 86462
* x86 vector shuffle cleanup/fixes:Nate Begeman2009-11-071-1/+1
| | | | | | | | 1. rename the movhp patfrag to movlhps, since thats what it actually matches 2. eliminate the bogus movhps load and store patterns, they were incorrect. The load transforms are already handled (correctly) by shufps/unpack. 3. revert a recent test change to its correct form. llvm-svn: 86415
* Add some dummy support for post-incremented loadsAnton Korobeynikov2009-11-071-0/+25
| | | | llvm-svn: 86385
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