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* Add 8 bit libcalls and make use of them for msp430Anton Korobeynikov2009-11-071-0/+22
| | | | llvm-svn: 86384
* Initial support for addrmode handling. Tests by Brian Lucas!Anton Korobeynikov2009-11-076-2/+292
| | | | llvm-svn: 86382
* It turns out that the testcase in question uncovered subreg-handling bug.Anton Korobeynikov2009-11-071-0/+1
| | | | | | | Add assert in asmprinter to catch such cases and xfail the tests. PR is to be filled. llvm-svn: 86375
* Fix a couple of shuffle patterns to use movhlps insteadEric Christopher2009-11-072-3/+4
| | | | | | | of movhps as the constraint. Changes optimizations so update testcases as appropriate as well. llvm-svn: 86360
* Fix PR5421 by APInt'izing switch lowering.Chris Lattner2009-11-071-2/+16
| | | | llvm-svn: 86354
* merge cmp1 into cmp0 and filecheckize.Chris Lattner2009-11-072-9/+19
| | | | llvm-svn: 86345
* Refactor code. Fix a potential missing check. Teach isIdentical() about ↵Evan Cheng2009-11-072-0/+42
| | | | | | tLDRpci_pic. llvm-svn: 86330
* - Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdenticalEvan Cheng2009-11-071-4/+6
| | | | | | | | | | except it doesn't care if the definitions' virtual registers differ. This is used by machine LICM and other MI passes to perform CSE. - Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical. Since pc relative constantpool entries are always different, this requires it it check if the values can actually the same. llvm-svn: 86328
* - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relativeEvan Cheng2009-11-062-4/+5
| | | | | | | | | | | | load of a GV from constantpool and then add pc. It allows the code sequence to be rematerializable so it would be hoisted by machine licm. - Add a late pass to break these pseudo instructions into a number of real instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm to this pass. This is done before post regalloc scheduling to allow the scheduler to proper schedule these instructions. It also allow them to be if-converted and shrunk by later passes. llvm-svn: 86304
* Honour subreg machine operands during asmprintingAnton Korobeynikov2009-11-061-0/+64
| | | | llvm-svn: 86303
* Print VMOV (immediate) operands as hexadecimal values. Apple's assemblerBob Wilson2009-11-061-0/+20
| | | | | | | | | will not accept negative values for these. LLVM's default operand printing sign extends values, so that valid unsigned values appear as negative immediates. Print all VMOV immediate operands as hex values to resolve this. Radar 7372576. llvm-svn: 86301
* Fix a broken test.Bob Wilson2009-11-061-1/+1
| | | | llvm-svn: 86298
* Remove ARMPCLabelIndex from ARMISelLowering. Use ↵Evan Cheng2009-11-061-4/+4
| | | | | | ARMFunctionInfo::createConstPoolEntryUId() instead. llvm-svn: 86294
* Fix PR5315, original patch by Nicolas Capens!Eric Christopher2009-11-064-18/+18
| | | | llvm-svn: 86203
* Update these tests for the new label names.Dan Gohman2009-11-052-7/+7
| | | | llvm-svn: 86192
* Add -mtriple to llc commands, attempting to fix buildbot failures.Bob Wilson2009-11-051-2/+2
| | | | llvm-svn: 86086
* Attempt again to fix buildbot failures: make expected output less specificBob Wilson2009-11-051-12/+9
| | | | | | and compile with -mtriple to specify *-apple-darwin targets. llvm-svn: 86081
* Add PowerPC codegen for indirect branches.Bob Wilson2009-11-041-0/+55
| | | | llvm-svn: 86050
* Fix broken test.Bob Wilson2009-11-041-2/+2
| | | | llvm-svn: 86045
* Add test for ARM indirectbr codegen.Bob Wilson2009-11-041-0/+63
| | | | llvm-svn: 86042
* RangeIsDefinedByCopyFromReg() should check for subreg_to_reg, insert_subreg,Evan Cheng2009-11-041-0/+15
| | | | | | | | and extract_subreg as a "copy" that defines a valno. Also fixes a typo. These two issues prevent a simple subreg coalescing from happening before. llvm-svn: 86022
* Fix test.Evan Cheng2009-11-041-1/+1
| | | | llvm-svn: 85986
* fconsts / fconstd immediate should be proceeded with #.Evan Cheng2009-11-031-4/+4
| | | | llvm-svn: 85952
* Re-apply 85799. It turns out my code isn't buggy.Evan Cheng2009-11-032-4/+6
| | | | llvm-svn: 85947
* Make opt default to not adding a target data string and update tests that ↵Kenneth Uildriks2009-11-031-0/+1
| | | | | | depend on target data to supply it within the test llvm-svn: 85900
* Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8.Evan Cheng2009-11-034-3/+64
| | | | llvm-svn: 85871
* Declare sin & cos as readonly so they match the code in SelectionDAGBuildNate Begeman2009-11-031-4/+4
| | | | llvm-svn: 85853
* Temporary xfail until PR5367 will be resolvedAnton Korobeynikov2009-11-032-0/+2
| | | | llvm-svn: 85848
* Revert r85049, it is causing PR5367Anton Korobeynikov2009-11-031-1/+1
| | | | llvm-svn: 85847
* Revert 85799 for now. It might be breaking llvm-gcc driver.Evan Cheng2009-11-022-6/+4
| | | | llvm-svn: 85827
* Initilize the machine LICM CSE map upon the first time an instruction is ↵Evan Cheng2009-11-022-4/+6
| | | | | | | | | | hoisted to the loop preheader. Add instructions which are already in the preheader block that may be common expressions of those that are hoisted out. These does get a few more instructions CSE'ed. llvm-svn: 85799
* Remove an irrelevant and poorly reduced test case.Evan Cheng2009-11-021-414/+0
| | | | llvm-svn: 85794
* Unbreak ARMBaseRegisterInfo::copyRegToReg.Evan Cheng2009-11-021-0/+29
| | | | llvm-svn: 85787
* Handle splats of undefs properly. This includes the testcase for PR5364 as well.Anton Korobeynikov2009-11-021-0/+20
| | | | llvm-svn: 85767
* 64-bit FP loads & stores operate on both NEON and VFP pipelines.Anton Korobeynikov2009-11-021-0/+37
| | | | llvm-svn: 85765
* Make use of imm12 version of Thumb2 ldr / str instructions more aggressively.Evan Cheng2009-11-011-0/+75
| | | | llvm-svn: 85743
* Fix tests.Evan Cheng2009-11-012-4/+4
| | | | llvm-svn: 85723
* improve x86 codegen support for blockaddress. We now compileChris Lattner2009-11-011-0/+16
| | | | | | | | | | | | | | | | | | | | | | the testcase into: _test1: ## @test1 ## BB#0: ## %entry leaq L_test1_bb6(%rip), %rax jmpq *%rax L_test1_bb: ## Address Taken LBB1_1: ## %bb movb $1, %al ret L_test1_bb6: ## Address Taken LBB1_2: ## %bb6 movb $2, %al ret Note, it is very very strange that BlockAddressSDNode doesn't carry around TargetFlags. Dan, please fix this. llvm-svn: 85703
* Use cbz and cbnz instructions.Evan Cheng2009-10-312-0/+34
| | | | llvm-svn: 85698
* vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid usingJim Grosbach2009-10-313-4/+6
| | | | | | them for scalar floating point operations for now. llvm-svn: 85697
* Consolidate test filesJim Grosbach2009-10-314-122/+100
| | | | llvm-svn: 85696
* Change to use FileCheckJim Grosbach2009-10-311-1/+3
| | | | llvm-svn: 85695
* Make tests more explicit about which instructions are expected.Jim Grosbach2009-10-311-2/+2
| | | | llvm-svn: 85694
* Grammar tweak to commentsJim Grosbach2009-10-311-4/+4
| | | | llvm-svn: 85693
* Update test to be more explicit about what instruction sequences are ↵Jim Grosbach2009-10-311-26/+39
| | | | | | expected for each operation. llvm-svn: 85691
* Update test to be more explicit about what instruction sequences are ↵Jim Grosbach2009-10-311-3/+16
| | | | | | expected for each operation. llvm-svn: 85689
* Expand 64-bit logical shift right inlineJim Grosbach2009-10-311-1/+1
| | | | llvm-svn: 85687
* Expand 64-bit arithmetic shift right inlineJim Grosbach2009-10-311-1/+1
| | | | llvm-svn: 85685
* Force triple; darwin's ASM syntax differs from linux's.Benjamin Kramer2009-10-311-1/+1
| | | | llvm-svn: 85676
* Expand 64 bit left shift inline rather than using the libcall. For now, thisJim Grosbach2009-10-311-1/+1
| | | | | | | is unconditional. Making it still use the libcall when optimizing for size would be a good adjustment. llvm-svn: 85675
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