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* Fix typoEli Bendersky2013-02-191-1/+1
| | | | llvm-svn: 175530
* Fix GCMetadaPrinter::finishAssembly not executed, patch by Yiannis Tsiouris.Benjamin Kramer2013-02-191-0/+31
| | | | | | | | | | | Due to the execution order of doFinalization functions, the GC information were deleted before AsmPrinter::doFinalization was executed. Thus, the GCMetadataPrinter::finishAssembly was never called. The patch fixes that by moving the code of the GCInfoDeleter::doFinalization to Printer::doFinalization. llvm-svn: 175528
* ARM NEON: Merge a f32 bitcast of a v2i32 extracteltArnold Schwaighofer2013-02-191-0/+25
| | | | | | | | | | | | | | A vectorized sitfp on doubles will get scalarized to a sequence of an extract_element of <2 x i32>, a bitcast to f32 and a sitofp. Due to the the extract_element, and the bitcast we will uneccessarily generate moves between scalar and vector registers. The patch fixes this by using a COPY_TO_REGCLASS and a EXTRACT_SUBREG to extract the element from the vector instead. radar://13191881 llvm-svn: 175520
* Expand pseudos/macros BteqzT8SltiX16, BteqzT8SltiuX16,Reed Kotler2013-02-192-0/+184
| | | | | | BtnezT8SltiX16, BtnezT8SltiuX16 . llvm-svn: 175486
* Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.Reed Kotler2013-02-192-0/+198
| | | | llvm-svn: 175474
* Comment out the rdar number.Chad Rosier2013-02-181-1/+1
| | | | llvm-svn: 175460
* [fast-isel] Remove an invalid assert.Chad Rosier2013-02-181-0/+7
| | | | | | | | If the memcpy has an odd length with an alignment of 2, this would incorrectly assert on the last 1 byte copy. rdar://13202135 llvm-svn: 175459
* Support for HiPE-compatible code emission, patch by Yiannis Tsiouris.Benjamin Kramer2013-02-181-0/+67
| | | | llvm-svn: 175457
* R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad patternVincent Lejeune2013-02-181-0/+19
| | | | llvm-svn: 175446
* Expand macro/pseudo instructions BtnezT8SltX16 and BtnezT8SltuX16.Reed Kotler2013-02-181-0/+96
| | | | llvm-svn: 175420
* Expand pseudo/macro BteqzT8SltX16.Reed Kotler2013-02-181-0/+98
| | | | llvm-svn: 175417
* Expand macro/pseudo BteqzT8CmpX16.Reed Kotler2013-02-181-0/+96
| | | | llvm-svn: 175416
* Beginning of expanding all current mips16 macro/pseudo instruction sequences.Reed Kotler2013-02-181-0/+95
| | | | | | | | | | This expansion will be moved to expandISelPseudos as soon as I can figure out how to do that. There are other instructions which use this ExpandFEXT_T8I816_ins and as soon as I have finished expanding them all, I will delete the macro asm string text so it has no way to be used in the future. llvm-svn: 175413
* Force a cpu for test. It failed on atom due to different scheduling decisions.Benjamin Kramer2013-02-171-1/+1
| | | | llvm-svn: 175401
* Replace "check:" wth "CHECK:".Jakub Staszak2013-02-161-4/+4
| | | | | | Also fix one test by changing "vpermilps" to "vpshufd". llvm-svn: 175357
* Reinitialize the ivars in the subtarget so that they can be reset with the ↵Bill Wendling2013-02-161-1/+0
| | | | | | new features. llvm-svn: 175336
* [ms-inline asm] Do not omit the frame pointer if we have ms-inline assembly.Chad Rosier2013-02-161-2/+8
| | | | | | | | | | | If the frame pointer is omitted, and any stack changes occur in the inline assembly, e.g.: "pusha", then any C local variable or C argument references will be incorrect. I pass no judgement on anyone who would do such a thing. ;) rdar://13218191 llvm-svn: 175334
* Temporary revert of 175320.Bill Wendling2013-02-151-0/+1
| | | | llvm-svn: 175322
* Reinitialize the ivars in the subtarget.Bill Wendling2013-02-151-0/+66
| | | | | | | When we're recalculating the feature set of the subtarget, we need to have the ivars in their initial state. llvm-svn: 175320
* enable SDISel sincos optimization for GNU environmentsPaul Redmond2013-02-151-14/+40
| | | | | | | | | | | | - add sincos to runtime library if target triple environment is GNU - added canCombineSinCosLibcall() which checks that sincos is in the RTL and if the environment is GNU then unsafe fpmath is enabled (required to preserve errno) - extended sincos-opt lit test Reviewed by: Hal Finkel llvm-svn: 175283
* AArch64: remove ConstantIsland pass & put literals in separate section.Tim Northover2013-02-159-31/+38
| | | | | | | | This implements the review suggestion to simplify the AArch64 backend. If we later discover that we *really* need the extra complexity of the ConstantIslands pass for performance reasons it can be resurrected. llvm-svn: 175258
* AArch64: refactor frame handling to use movz/movk for overlarge offsets.Tim Northover2013-02-151-18/+15
| | | | | | | | In the near future litpools will be in a different section, which means that any access to them is at least two instructions. This makes the case for a movz/movk pair (if total offset <= 32-bits) even more compelling. llvm-svn: 175257
* Fix minor mips16 issues in directives for function prologue. Probably this doesReed Kotler2013-02-151-4/+20
| | | | | | | not matter but makes it more gcc compatible which avoids possible subtle problems. Also, turned back on a disabled check in helloworld.ll. llvm-svn: 175237
* Dont merge consecutive loads/stores into vectors when noimplicitfloat is used.Nadav Rotem2013-02-141-0/+34
| | | | llvm-svn: 175190
* Re-apply r175088 for bug fix 13622: Add paired register support forWeiming Zhao2013-02-142-2/+55
| | | | | | | | inline asm with 64-bit data on ARM Update test case to use -mtriple=arm-linux-gnueabi llvm-svn: 175186
* R600: Do not fold single instruction with more that 3 kcache readVincent Lejeune2013-02-141-0/+52
| | | | | | | | | It fixes around 100 tfb piglit tests and 16 glean tests. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175183
* Make ARMAsmParser accept the correct alignment specifier syntax in instructions.Kristof Beyls2013-02-141-1/+1
| | | | | | | | | The parser will now accept instructions with alignment specifiers written like vld1.8 {d16}, [r0:64] , while also still accepting the incorrect syntax vld1.8 {d16}, [r0, :64] llvm-svn: 175164
* Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).Elena Demikhovsky2013-02-141-0/+14
| | | | | | Added a test. llvm-svn: 175144
* R600: Add lit tests for texture sampling instruction selection.Michel Danzer2013-02-142-0/+113
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175138
* Reapply "s/grep/FileCheck/ in some tests"Andrew Trick2013-02-145-6/+15
| | | | | | | | This reverts commit fd1335e982bbf93c5f450ed4fd29f9f787435c85. Use a triple this time. llvm-svn: 175134
* Revert "s/grep/FileCheck/ in some tests"Andrew Trick2013-02-145-16/+6
| | | | | | | | | | | | | | | | | | This reverts commit 8b75e6bc35fb3f9c1e788dbd05084c0f4a60a0f3. The FileCheck tests are not equivalent: test/CodeGen/X86/tailcall-structret.ll:6:10: error: expected string not found in input ; CHECK: jmp init ^ <stdin>:1:2: note: scanning from here .section __TEXT,__text,regular,pure_instructions ^ <stdin>:13:2: note: possible intended match here jmp _init ## TAILCALL ^ llvm-svn: 175124
* temporarily revert the patch due to some conflictsWeiming Zhao2013-02-132-55/+2
| | | | llvm-svn: 175107
* Hexagon: add support for predicate-GPR copies.Anshuman Dasgupta2013-02-131-0/+8
| | | | llvm-svn: 175102
* R600: Add support for 128-bit parametersTom Stellard2013-02-131-0/+18
| | | | | NOTE: This is a candidate for the Mesa stable branch. llvm-svn: 175096
* s/grep/FileCheck/ in some testsEli Bendersky2013-02-131-1/+2
| | | | llvm-svn: 175093
* s/grep/FileCheck/ in some testsEli Bendersky2013-02-135-6/+16
| | | | llvm-svn: 175089
* Bug fix 13622: Add paired register support for inline asm with 64-bit data ↵Weiming Zhao2013-02-132-2/+55
| | | | | | on ARM llvm-svn: 175088
* [ms-inline asm] Fix up test case for non-Darwin platforms.Chad Rosier2013-02-131-1/+1
| | | | llvm-svn: 175087
* Hexagon: Use absolute addressing mode loads/stores for global+offset Jyotsna Verma2013-02-132-0/+86
| | | | | | instead of redefining separate instructions for them. llvm-svn: 175086
* [ms-inline-asm] Add support for memory references that have non-immediateChad Rosier2013-02-131-0/+23
| | | | | | | displacements. rdar://12974533 llvm-svn: 175083
* For Mips 16, add the optimization where the 16 bit form of addiu sp can be usedReed Kotler2013-02-131-0/+31
| | | | | | | | | | if the offset fits in 11 bits. This makes use of the fact that the abi requires sp to be 8 byte aligned so the actual offset can fit in 8 bits. It will be shifted left and sign extended before being actually used. The assembler or direct object emitter will shift right the 11 bit signed field by 3 bits. We don't need to deal with that here. llvm-svn: 175073
* PR14992 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIADavid Peixotto2013-02-131-0/+28
| | | | | | | Fixed bug in tablegen conversion when source pseudo instruction has a different number of arguments than the destination instruction. llvm-svn: 175066
* X86: Disable generation of rep;movsl when %esi is used as a base pointer.Benjamin Kramer2013-02-131-0/+18
| | | | | | | | | | | This happens when there is both stack realignment and a dynamic alloca in the function. If we overwrite %esi (rep;movsl uses fixed registers) we'll lose the base pointer and the next register spill will write into oblivion. Fixes PR15249 and unbreaks firefox on i386/freebsd. Mozilla uses dynamic allocas and freebsd a 4 byte stack alignment. llvm-svn: 175057
* Make jumptables work for -staticReed Kotler2013-02-131-0/+71
| | | | llvm-svn: 175044
* Prevent insertion of "vzeroupper" before call that preserves YMM registers, ↵Elena Demikhovsky2013-02-131-0/+40
| | | | | | since a caller uses preserved registers across the call. llvm-svn: 175043
* Check i1 as well as i8 variables for 8 bit registers for x86 inlineEric Christopher2013-02-131-0/+31
| | | | | | assembly. llvm-svn: 175036
* Finish obviously broken thought.Eric Christopher2013-02-131-1/+1
| | | | llvm-svn: 175035
* Fix the lit test added in r174972Paul Redmond2013-02-121-2/+2
| | | | | | Patch by: Kevin Schoedel llvm-svn: 174974
* Hexagon: Add support to generate predicated absolute addressing modeJyotsna Verma2013-02-121-0/+19
| | | | | | instructions. llvm-svn: 174973
* PR14562 - Truncation of left shift became undefPaul Redmond2013-02-121-0/+15
| | | | | | | | | | | DAGCombiner::ReduceLoadWidth was converting (trunc i32 (shl i64 v, 32)) into (shl i32 v, 32) into undef. To prevent this, check the shift count against the final result size. Patch by: Kevin Schoedel Reviewed by: Nadav Rotem llvm-svn: 174972
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