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* [NVPTX] Disable vector registersJustin Holewinski2013-02-121-0/+66
| | | | | | | | | | | Vectors were being manually scalarized by the backend. Instead, let the target-independent code do all of the work. The manual scalarization was from a time before good target-independent support for scalarization in LLVM. However, this forces us to specially-handle vector loads and stores, which we can turn into PTX instructions that produce/consume multiple operands. llvm-svn: 174968
* ARM NEON: Handle v16i8 and v8i16 reverse shufflesArnold Schwaighofer2013-02-121-0/+27
| | | | | | | | | | | | | | | Lower reverse shuffles to a vrev64 and a vext instruction instead of the default legalization of storing and loading to the stack. This is important because we generate reverse shuffles in the loop vectorizer when we reverse store to an array. uint8_t Arr[N]; for (i = 0; i < N; ++i) Arr[N - i - 1] = ... radar://13171760 llvm-svn: 174929
* Extend Hexagon hardware loop generation to handle various additional cases:Krzysztof Parzyszek2013-02-117-0/+1528
| | | | | | | | - variety of compare instructions, - loops with no preheader, - arbitrary lower and upper bounds. llvm-svn: 174904
* [NVPTX] Remove NoCapture from address space conversion intrinsics. NoCapture ↵Justin Holewinski2013-02-111-0/+21
| | | | | | is not valid in this case, and was causing incorrect optimizations. llvm-svn: 174896
* Add the 16 bit version of addiu. To the assembler, the 16 and 32 bit are theReed Kotler2013-02-081-0/+30
| | | | | | | | | | same so we put in the comment field an indicator when we think we are emitting the 16 bit version. For the direct object emitter, the difference is important as well as for other passes which need an accurate count of program size. There will be other similar putbacks to this for various instructions. llvm-svn: 174747
* DAGCombiner: Constant folding around pre-increment loads/storesHal Finkel2013-02-081-0/+47
| | | | | | | | | | | Previously, even when a pre-increment load or store was generated, we often needed to keep a copy of the original base register for use with other offsets. If all of these offsets are constants (including the offset which was combined into the addressing mode), then this is clearly unnecessary. This change adjusts these other offsets to use the new incremented address. llvm-svn: 174746
* Revert 172027 and 174336. Remove diagnostics about over-aligned stack objects.Bob Wilson2013-02-082-20/+1
| | | | | | | | | | | | Aside from the question of whether we report a warning or an error when we can't satisfy a requested stack object alignment, the current implementation of this is not good. We're not providing any source location in the diagnostics and the current warning is not connected to any warning group so you can't control it. We could improve the source location somewhat, but we can do a much better job if this check is implemented in the front-end, so let's do that instead. <rdar://problem/13127907> llvm-svn: 174741
* When Mips16 frames grow large, the immediate field may exceed the maximumReed Kotler2013-02-081-0/+61
| | | | | | | | allowed size for the instruction. This code uses RegScavenger to fix this. We sometimes need 2 registers for Mips16 so we must handle things differently than how register scavenger is normally used. llvm-svn: 174696
* R600: Add support for SET*_DX10 instructionsTom Stellard2013-02-073-15/+150
| | | | | | | | | | | These instructions compare two floating point values and return an integer true (-1) or false (0) value. When compiling code generated by the Mesa GLSL frontend, the SET*_DX10 instructions save us four instructions for most branch decisions that use floating-point comparisons. llvm-svn: 174609
* R600: Add tests for unsupported condition codes.Tom Stellard2013-02-071-0/+83
| | | | | | All of the le and lt variants are unsupported. llvm-svn: 174608
* R600: Fix assembly name for SETGT_INTTom Stellard2013-02-071-1/+1
| | | | llvm-svn: 174607
* Make sure we call externals from libraries properly when -static.Reed Kotler2013-02-071-0/+13
| | | | | | For example, when we are doing mips16 hard float or soft float. llvm-svn: 174583
* Enable jumps when in -static mode.Reed Kotler2013-02-071-0/+4
| | | | llvm-svn: 174580
* This is a follow-up on r174446, now taking Atom processors intoEli Bendersky2013-02-061-0/+31
| | | | | | | | | | | | account. Atoms use LEA for updating SP in prologs/epilogs, and the exact LEA opcode depends on the data model. Also reapplying the test case which was added and then reverted (because of Atom failures), this time specifying explicitly the CPU in addition to the triple. The test case now checks all variations (data mode, cpu Atom vs. Core). llvm-svn: 174542
* Implement external weak (ELF) symbols on AArch64Tim Northover2013-02-061-0/+13
| | | | | | | | | Weakly defined symbols should evaluate to 0 if they're undefined at link-time. This is impossible to do with the usual address generation patterns, so we should use a literal pool entry to materlialise the address. llvm-svn: 174518
* Remove this test in the meantime, since it won't pass on Atom. Atom uses leaEli Bendersky2013-02-061-22/+0
| | | | | | | to move the stack pointer in prologs/epilogs. I will fix the test and add it back later. llvm-svn: 174484
* Attempt to recover gdb bot after r174445.Manman Ren2013-02-064-4/+4
| | | | | | | | | Failure: undefined symbol 'Lline_table_start0'. Root-cause: we use a symbol subtraction to calculate at_stmt_list, but the line table entries are not dumped in the assembly. Fix: use zero instead of a symbol subtraction for Compile Unit 0. llvm-svn: 174479
* Test for r174446Eli Bendersky2013-02-051-0/+22
| | | | llvm-svn: 174464
* Dwarf: support for LTO where a single object file can have multiple line tablesManman Ren2013-02-055-5/+5
| | | | | | | | | We generate one line table for each compilation unit in the object file. Reviewed by Eric and Kevin. rdar://problem/13067005 llvm-svn: 174445
* [mips] Do not use function CC_MipsN_VarArg unless the function being analyzedAkira Hatanaka2013-02-051-0/+14
| | | | | | | | | | | is a vararg function. The original code was examining flag OutputArg::IsFixed to determine whether CC_MipsN_VarArg or CC_MipsN should be called. This is not correct, since this flag is often set to false when the function being analyzed is a non-variadic function. llvm-svn: 174442
* Reapply r174343, with a fix for a scary DAG combine bug where it failed to ↵Owen Anderson2013-02-052-4/+5
| | | | | | | | | | | | | | | | | | differentiate between the alignment of the base point of a load, and the overall alignment of the load. This caused infinite loops in DAG combine with the original application of this patch. ORIGINAL COMMIT LOG: When the target-independent DAGCombiner inferred a higher alignment for a load, it would replace the load with one with the higher alignment. However, it did not place the new load in the worklist, which prevented later DAG combines in the same phase (for example, target-specific combines) from ever seeing it. This patch corrects that oversight, and updates some tests whose output changed due to slightly different DAGCombine outputs. llvm-svn: 174431
* Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handleJyotsna Verma2013-02-053-0/+322
| | | | | | zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns. llvm-svn: 174429
* Hexagon: Add testcase for post-increment store instructions.Jyotsna Verma2013-02-051-0/+29
| | | | llvm-svn: 174419
* [SjLj Prepare] When demoting an invoke instructions to the stack, if the normalChad Rosier2013-02-051-0/+67
| | | | | | | edge is critical, then split it so we can insert the store. rdar://13126179 llvm-svn: 174418
* Hexagon: Use multiclass for absolute addressing mode stores.Jyotsna Verma2013-02-051-0/+46
| | | | llvm-svn: 174412
* Add a test case for PR14750.Jakob Stoklund Olesen2013-02-051-2/+40
| | | | | | This was fixed by r174402. llvm-svn: 174405
* R600: Add tests for instruction predicatesTom Stellard2013-02-051-0/+100
| | | | llvm-svn: 174393
* R600: Emit function name in the AsmPrinterTom Stellard2013-02-054-2/+15
| | | | | | | | Emitting the function name allows us to check for it in the FileCheck tests so we can make sure FileCheck is checking the output of the correct function. llvm-svn: 174392
* Hexagon: Add V4 compare instructions. Enable relationship mappingJyotsna Verma2013-02-052-0/+77
| | | | | | for the existing instructions. llvm-svn: 174389
* Revert r174343, "When the target-independent DAGCombiner inferred a higher ↵NAKAMURA Takumi2013-02-052-5/+4
| | | | | | | | alignment for a load," It caused hangups in compiling clang/lib/Parse/ParseDecl.cpp and clang/lib/Driver/Tools.cpp in stage2 on some hosts. llvm-svn: 174374
* Link .ARM.exidx with corresponding text section.Logan Chien2013-02-051-0/+47
| | | | | | | | The sh_link in the ELF section header of .ARM.exidx should be filled with the section index of the corresponding text section. llvm-svn: 174372
* This patch that sets the EmitAlias flag in td files Jack Carter2013-02-051-2/+2
| | | | | | | | | | | | | and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic llvm-svn: 174358
* When the target-independent DAGCombiner inferred a higher alignment for a load,Owen Anderson2013-02-052-4/+5
| | | | | | | | | | | it would replace the load with one with the higher alignment. However, it did not place the new load in the worklist, which prevented later DAG combines in the same phase (for example, target-specific combines) from ever seeing it. This patch corrects that oversight, and updates some tests whose output changed due to slightly different DAGCombine outputs. llvm-svn: 174343
* [Stack Alignment] emit warning instead of a hard errorManman Ren2013-02-041-2/+2
| | | | | | | | | | | Per discussion in rdar://13127907, we should emit a hard error only if people write code where the requested alignment is larger than achievable and assumes the low bits are zeros. A warning should be good enough when we are not sure if the source code assumes the low bits are zeros. rdar://13127907 llvm-svn: 174336
* Hexagon: Add V4 combine instructions and some more Def Pats for V2.Jyotsna Verma2013-02-042-1/+56
| | | | llvm-svn: 174331
* Disable a couple more vector splat optimizations on PPC.Benjamin Kramer2013-02-041-1/+41
| | | | | | | I didn't see those because the test case used "not grep". FileCheck the test and XFAIL it, preserving the old optimization, so this can be fixed eventually. llvm-svn: 174330
* X86: Open up some opportunities for constant folding by postponing shift ↵Benjamin Kramer2013-02-041-0/+10
| | | | | | | | lowering. Fixes PR15141. llvm-svn: 174327
* SelectionDAG: Teach FoldConstantArithmetic how to deal with vectors.Benjamin Kramer2013-02-044-7/+7
| | | | | | | | | | | | | | | | | This required disabling a PowerPC optimization that did the following: input: x = BUILD_VECTOR <i32 16, i32 16, i32 16, i32 16> lowered to: tmp = BUILD_VECTOR <i32 8, i32 8, i32 8, i32 8> x = ADD tmp, tmp The add now gets folded immediately and we're back at the BUILD_VECTOR we started from. I don't see a way to fix this currently so I left it disabled for now. Fix some trivially foldable X86 tests too. llvm-svn: 174325
* Remove the (apparently) unnecessary debug info metadata indirection.David Blaikie2013-02-023-14/+7
| | | | | | | | | | The main lists of debug info metadata attached to the compile_unit had an extra layer of metadata nodes they went through for no apparent reason. This patch removes that (& still passes just as much of the GDB 7.5 test suite). If anyone can show evidence as to why these extra metadata nodes are there I'm open to reverting this patch & documenting why they're there. llvm-svn: 174266
* Start static relocation implementation for mips16.Reed Kotler2013-02-021-0/+7
| | | | | | This checkin makes hello world work. llvm-svn: 174264
* rdar://13126763Shuxin Yang2013-02-021-0/+42
| | | | | | | Fix a bug in DAGCombine. The symptom is mistakenly optimizing expression "x + x*x" into "x * 3.0". llvm-svn: 174239
* LLVM enablement for some older PowerPC CPUsBill Schmidt2013-02-011-0/+14
| | | | llvm-svn: 174230
* Two changes relevant to LEA and x32:David Sehr2013-02-012-0/+41
| | | | | | | | | 1) allows the use of RIP-relative addressing in 32-bit LEA instructions under x86-64 (ILP32 and LP64) 2) separates the size of address registers in 64-bit LEA instructions from control by ILP32/LP64. llvm-svn: 174208
* Hexagon: Test case to confirm generation of indexed loads with zero offset.Jyotsna Verma2013-02-011-0/+70
| | | | llvm-svn: 174196
* Add explicit triples to AArch64 testsTim Northover2013-02-0171-76/+76
| | | | | | | | Only Linux is supported at the moment, and other platforms quickly fault. As a result these tests would fail on non-Linux hosts. It may be worth making the tests more generic again as more platforms are supported. llvm-svn: 174170
* R600: Fold clamp, neg, absTom Stellard2013-01-311-2/+1
| | | | | | | Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174099
* When lowering memcpys to loads and stores, make sure we don't promote alignmentsLang Hames2013-01-311-25/+52
| | | | | | past the natural stack alignment. llvm-svn: 174085
* Add AArch64 as an experimental target.Tim Northover2013-01-3179-0/+8606
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. llvm-svn: 174054
* Check and allow floating point registers to select the size of theEric Christopher2013-01-311-0/+42
| | | | | | | register for inline asm. This conforms to how gcc allows for effective casting of inputs into gprs (fprs is already handled). llvm-svn: 174008
* Replace some more greps with FileChecks in testsEli Bendersky2013-01-313-22/+30
| | | | llvm-svn: 174006
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