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* Re-enable test o32_cc_vararg.ll.Akira Hatanaka2011-04-151-3/+0
| | | | llvm-svn: 129616
* Add ORR and EOR to the CMP peephole optimizer. It's hard to get isel to generateCameron Zwarich2011-04-151-3/+22
| | | | | | a case involving EOR, so I only added a test for ORR. llvm-svn: 129610
* Add this test back for Darwin.Rafael Espindola2011-04-151-0/+10
| | | | llvm-svn: 129607
* The AND instruction leaves the V flag unmodified, so it falls victim to the sameCameron Zwarich2011-04-151-0/+22
| | | | | | problem as all of the other instructions we fold with CMPs. llvm-svn: 129602
* Add missing register forms of instructions to the ARM CMP-folding code. ThisCameron Zwarich2011-04-151-0/+22
| | | | | | fixes <rdar://problem/9287901>. llvm-svn: 129599
* Add pass that expands pseudo instructions into target instructions after ↵Akira Hatanaka2011-04-152-0/+30
| | | | | | register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions. llvm-svn: 129594
* Add 129518 back with a fix for when we are producing eh just because of ↵Rafael Espindola2011-04-153-15/+4
| | | | | | | | | debug info. Change ELF systems to use CFI for producing the EH tables. This reduces the size of the clang binary in Debug builds from 690MB to 679MB. llvm-svn: 129571
* Revert r129518, "Change ELF systems to use CFI for producing the EH tables. ↵NAKAMURA Takumi2011-04-153-4/+15
| | | | | | | | This reduces the" It broke several builds. llvm-svn: 129557
* Fix another fcopysign lowering bug. If src is f64 and destination is f32, don'tEvan Cheng2011-04-151-4/+21
| | | | | | forget to right shift the source by 32 first. rdar://9287902 llvm-svn: 129556
* Add 3DNow! intrinsics.Michael J. Spencer2011-04-151-0/+297
| | | | llvm-svn: 129551
* Follow up on r127913. Fix Thumb revsh isel. rdar://9286766Evan Cheng2011-04-141-0/+56
| | | | llvm-svn: 129548
* Change ELF systems to use CFI for producing the EH tables. This reduces theRafael Espindola2011-04-143-15/+4
| | | | | | size of the clang binary in Debug builds from 690MB to 679MB. llvm-svn: 129518
* In the pre-RA scheduler, maintain cmp+br proximity.Andrew Trick2011-04-145-9/+74
| | | | | | | | | | | | | | | | | | | | | | | | This is done by pushing physical register definitions close to their use, which happens to handle flag definitions if they're not glued to the branch. This seems to be generally a good thing though, so I didn't need to add a target hook yet. The primary motivation is to generate code closer to what people expect and rule out missed opportunity from enabling macro-op fusion. As a side benefit, we get several 2-5% gains on x86 benchmarks. There is one regression: SingleSource/Benchmarks/Shootout/lists slows down be -10%. But this is an independent scheduler bug that will be tracked separately. See rdar://problem/9283108. Incidentally, pre-RA scheduling is only half the solution. Fixing the later passes is tracked by: <rdar://problem/8932804> [pre-RA-sched] on x86, attempt to schedule CMP/TEST adjacent with condition jump Fixes: <rdar://problem/9262453> Scheduler unnecessary break of cmp/jump fusion llvm-svn: 129508
* As Dan pointed out, movzbl, movsbl, and friends are nicer than their aliasBill Wendling2011-04-1427-82/+73
| | | | | | (movzx/movsx) because they give more information. Revert that part of the patch. llvm-svn: 129498
* Have the X86 back-end emit the alias instead of what's being aliased. In mostBill Wendling2011-04-1429-82/+91
| | | | | | cases, it's much nicer and more informative reading the alias. llvm-svn: 129497
* Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>.Cameron Zwarich2011-04-131-0/+18
| | | | llvm-svn: 129468
* Fix a regression caused by r102515 where explicit alignment on globals isCameron Zwarich2011-04-132-5/+5
| | | | | | | ignored. There was a test to catch this, but it was just blindly updated in a large change. This fixes another part of <rdar://problem/9275290>. llvm-svn: 129466
* Fix an obvious problem with an alignment computation. AsmPrinter actually doesCameron Zwarich2011-04-131-0/+2
| | | | | | | the max itself, so it is not easy to write a test case for this, but I added a test case that would fail if the code in AsmPrinter were removed. llvm-svn: 129432
* If a global variable has a specified alignment that is less than the preferredCameron Zwarich2011-04-131-0/+9
| | | | | | | alignment for its type, use the minimum of the specified alignment and the ABI alignment. This fixes <rdar://problem/9275290>. llvm-svn: 129428
* Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor ↵Andrew Trick2011-04-136-27/+25
| | | | | | | | | | | | | | | | | | | | | latency. Additional fixes: Do something reasonable for subtargets with generic itineraries by handle node latency the same as for an empty itinerary. Now nodes default to unit latency unless an itinerary explicitly specifies a zero cycle stage or it is a TokenFactor chain. Original fixes: UnitsSharePred was a source of randomness in the scheduler: node priority depended on the queue data structure. I rewrote the recent VRegCycle heuristics to completely replace the old heuristic without any randomness. To make the ndoe latency adjustments work, I also needed to do something a little more reasonable with TokenFactor. I gave it zero latency to its consumers and always schedule it as low as possible. llvm-svn: 129421
* Reapply r129401 with patch for clang.Bill Wendling2011-04-131-2/+2
| | | | llvm-svn: 129419
* Temporarily revert r129408 to see if it brings the bots back.Eric Christopher2011-04-131-15/+0
| | | | llvm-svn: 129417
* Fix a bug where we were counting the alias sets as completely usedEric Christopher2011-04-121-0/+15
| | | | | | | | registers for fast allocation. Fixes rdar://9207598 llvm-svn: 129408
* Revert r129401 for now. Clang is using the old way of doing things.Bill Wendling2011-04-121-2/+2
| | | | llvm-svn: 129403
* Remove the unaligned load intrinsics in favor of using native unaligned loads.Bill Wendling2011-04-121-2/+2
| | | | | | | | | Now that we have a first-class way to represent unaligned loads, the unaligned load intrinsics are superfluous. First part of <rdar://problem/8460511>. llvm-svn: 129401
* Revert 129383. It causes some targets to hit a scheduler assert.Andrew Trick2011-04-122-4/+6
| | | | llvm-svn: 129385
* PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.Andrew Trick2011-04-122-6/+4
| | | | | | | | | | | | UnitsSharePred was a source of randomness in the scheduler: node priority depended on the queue data structure. I rewrote the recent VRegCycle heuristics to completely replace the old heuristic without any randomness. To make these heuristic adjustments to node latency work, I also needed to do something a little more reasonable with TokenFactor. I gave it zero latency to its consumers and always schedule it as low as possible. llvm-svn: 129383
* Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARMCameron Zwarich2011-04-121-1/+1
| | | | | | | stores of arguments in the same cache line. This fixes the second half of <rdar://problem/8674845>. llvm-svn: 129345
* Add scheduling information for the MBlaze backend.Wesley Peck2011-04-112-15/+9
| | | | llvm-svn: 129311
* Look pass copies when determining whether hoisting would end up inserting ↵Evan Cheng2011-04-111-0/+34
| | | | | | more copies. rdar://9266679 llvm-svn: 129297
* look for the verboten argument slot access in any order, thanks to FritsChris Lattner2011-04-091-0/+1
| | | | | | for pointing this out llvm-svn: 129217
* Fix a bug where RecursivelyDeleteTriviallyDeadInstructions couldChris Lattner2011-04-091-0/+28
| | | | | | | delete the instruction pointed to by CGP's current instruction iterator, leading to a crash on the testcase. This fixes PR9578. llvm-svn: 129200
* fix two completely broken tests, which were matching due to PR9629.Chris Lattner2011-04-092-4/+4
| | | | llvm-svn: 129195
* remove a bunch of CHECK lines that aren't checking whatChris Lattner2011-04-091-5/+0
| | | | | | | they thought they were, because alternation was expanding wrong in {{}}'s. llvm-svn: 129194
* have dag combine zap "store undef", which can be formed during call loweringChris Lattner2011-04-091-0/+15
| | | | | | with undef arguments. llvm-svn: 129185
* don't test for codegen of 'store undef'Chris Lattner2011-04-092-7/+11
| | | | llvm-svn: 129184
* Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap ↵Evan Cheng2011-04-081-1/+1
| | | | | | is lowered into a call to the specified trap function at sdisel time. llvm-svn: 129152
* Add option to emit @llvm.trap as a function call instead of a trap ↵Evan Cheng2011-04-071-3/+8
| | | | | | instruction. rdar://9249183. llvm-svn: 129107
* Added a check in the preRA scheduler for potential interference on aAndrew Trick2011-04-071-0/+31
| | | | | | | | | induction variable. The preRA scheduler is unaware of induction vars, so we look for potential "virtual register cycles" instead. Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing llvm-svn: 129100
* Fix handling of functions with internal linkage.Akira Hatanaka2011-04-071-0/+52
| | | | llvm-svn: 129099
* Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal ↵Tanya Lattner2011-04-071-0/+18
| | | | | | vector type (vectors of size 3). Also included test cases. llvm-svn: 129074
* Change -arm-divmod-libcall to a target neutral option.Evan Cheng2011-04-071-1/+1
| | | | llvm-svn: 129045
* Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for ↵Owen Anderson2011-04-061-0/+9
| | | | | | folded comparisons, just like ADD and SUB. llvm-svn: 129038
* These tests no longer require linear scan because reserved register ↵Jakob Stoklund Olesen2011-04-055-19/+14
| | | | | | coalescing is now universal. llvm-svn: 128936
* Run LiveDebugVariables in RegAllocBasic and RegAllocGreedy.Jakob Stoklund Olesen2011-04-059-1/+10
| | | | llvm-svn: 128935
* Fix one more batch of X86 tests to be register allocation dependent.Jakob Stoklund Olesen2011-04-059-2797/+2811
| | | | llvm-svn: 128919
* When dead code elimination removes all but one use, try to fold the single ↵Jakob Stoklund Olesen2011-04-051-0/+1
| | | | | | | | def into the remaining use. Rematerialization can leave single-use loads behind that we might as well fold whenever possible. llvm-svn: 128918
* Fix test-llvm failures.Johnny Chen2011-04-056-13/+13
| | | | llvm-svn: 128906
* ARM doesn't support byval yet. XFAIL this test until it does.Stuart Hastings2011-04-051-0/+1
| | | | llvm-svn: 128891
* Ensure all defs referring to a virtual register are marked dead by ↵Jakob Stoklund Olesen2011-04-051-1/+5
| | | | | | | | | | | | addRegisterDead(). There can be multiple defs for a single virtual register when they are defining sub-registers. The missing <dead> flag was stopping the inline spiller from eliminating dead code after rematerialization. llvm-svn: 128888
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